Novellus Systems Incorporated

Timothy Patrick Cleary

Steven T Mayer

Heung L Park

Thomas W Mountsier

Edmund Minshall

Daniel A Koos

Jonathan David Reid

Thomas Anand Ponnuswamy

Eric G Webb

John Derwood Herb

Michael John Janicki

John F Stumpf

Robert Marshall Stowell

Brian Severson

David T Marquardt

Rand Conner

Kevin Bertsch

James Jed Crawford

Franklin D Root

Jasent Montano

Electroless plating is performed to deposit conductive materials on work pieces such as partially fabricated integrated circuits. Components of an electroless plating bath are separately applied to a work piece by spin coating to produce a very thin conductive layer (in the range of a few hundred angstroms). The components are typically a reducing agent and a metal source.

Electroless layer plating process and apparatus

An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting. After the metal regions are etched and recessed in the substrate surface, a conductive capping layer is formed using electroless deposition over the recessed exposed metal regions.

Fabrication of semiconductor interconnect structure

Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage

Methods and apparatus are provided for the chemical mechanical planarization (CMP) of a surface of a work piece. In accordance with one embodiment of the invention the apparatus comprises a plurality of CMP systems, a plurality of load cups for loading unprocessed work pieces into and unloading processed work pieces from the plurality of CMP systems, a plurality of cleaning stations for cleaning processed work pieces unloaded from the CMP systems, and a single robot configured to transfer unprocessed work pieces to the plurality of load cups and to transfer processed work pieces from the load cups to the plurality of cleaning stations.

CMP apparatus and method

An apparatus for electrochemical treatment of a substrate, in particular for electroplating an integrated circuit wafer. An apparatus preferably includes dynamically operable concentric anodes and dielectric shields in an electrochemical bath. Preferably, the bath height of an electrochemical bath, the substrate height, and the shape and positions of an insert shield and a diffuser shield are dynamically variable during electrochemical treatment operations. Step include varying anode current, bath height and substrate height, shield shape, and shield position.

Electrochemical treatment of integrated circuit substrates using concentric anodes and variable field shaping elements

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Portland, OR, United States of America

Timothy Patrick Cleary