Cadence Design Systems, Inc.

Ausdia, Inc.

Timothy P Moore

Thaddeus Clay McCracken

Samuel S Appleton

Atul Bhagat

Disclosed is an improved method, system, and computer program product for performing core placement when presented with an I/O ring design. A multi-pass approach is taken to place and shape core objects into the available core area formed by the inner surface of the I/O ring. The multi-pass approach permits very fast placement of the core objects, which still provides for an accurate estimation of the die size and configuration requirements for the electronic design. Moreover, the present approach allows core objects to be placed in a way that retains any preferred affinities for the objects to be located near other objects, e.g., near specific I/Os on the I/O ring.

Method and system for implementing core placement

Systems and methods for identifying and managing the relationships between clock domains in an integrated circuit design are disclosed. A computer-implemented method analyzes the behavioral structure of the clock-to-clock logical relationships in a proposed integrated circuit design. In one embodiment, the method comprises receiving as inputs a description of the design (in a synthesizable format or a synthesized gate-level netlist and definitions of the clock waveforms and timing constraints used in the design, and automatically identifying the relationships between the clocks specified in the description and categorizing the relationships into a plurality of behavioral categories. A list of timing exceptions may optionally also be provided as an input. The identified relationships between clocks and the behavioral categories may be used to verify any existing timing exceptions between clock pairs, and/or to create any missing exceptions between the clock pairs.

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Mountain View, CA, United States of America

Timothy P Moore