Silicon Graphics, Incorporated

Mips Computer Systems, Inc.

Timothy P Layman

Allen W Roberts

George S Taylor

P Michael Farmwald

Huy X Ngo

A system and method for providing power to the gates of a semiconductor chip routes power and ground from one layer of the chip to another layer of the chip using a first metal strip located at a first metal layer and a second metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer. A stacked via is used to connect the first metal strip to the second metal strip. The stacked via may comprise, for example, a first via connecting the first metal strip to an intermediate metal strip and a second via connecting the intermediate metal strip to the second metal strip. Alternatively, the stacked via may comprise a plurality of vias connecting the first metal strip to the intermediate metal strip and a plurality of vias connecting the intermediate metal strip to the second metal strip. The system and method avoids using long, parallel metal strips on each layer of the chip to route power and ground from one layer of the chip to another layer of the chip.

System and method to provide power to a sea of gates standard cell block from an overhead bump grid

A method of invalidating a line in a designated cache in each level of a multiple level, multiple cache memory system. Each line of the cache memory system includes a tag field, a data field, and a bit indicative of the validity of the line. The method provides a software invalidate instruction which bypasses any address translation mechanism. Included in the software invalidate instruction is a first field to identify within which multiple cache the line is to be avoided. A target address is generated to index each level of the cache memory system. The state of the bit is changed in accordance with the address and the invalidate instruction.

Software invalidation in a multiple level, multiple cache system

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instruction and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a 'miss' is encountered in both the primary and secondary caches does the system processor access the main memory.

Cache memory system employing virtual address primary instruction and

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own separate tag directory. The primary caches use a virtual addressing scheme employing both virtual tags and virtual addresses. The secondary cache employs a hybrid addressing scheme which uses virtual tags and partial physical addresses. The primary and secondary caches operate in parallel unless the larger and slower secondary cache is busy performing a previous operation. Only if a 'miss' is encountered in both the primary and secondary caches does the system processor access the main memory.

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San Carlos, CA, United States of America

Timothy P Layman