International Business Machines Corporation

Globalfoundries Inc.

Timothy O Dickson

John Francis Bulzacchelli

Frank David Ferraiolo

Daniel Mark Dreps

Mounir Meghelli

Douglas James Joseph

Bongjin Kim

Daniel Joseph Friedman

Sergey Vladimirovich Rylov

Jonathan E Proesel

Martin Cochet

Zeynep Toprak-Deniz

Rui Yan Matthew Loh

Alexander V Rylyakov

Jieming Qi

Marcel A Kossel

Robert J Reese

Herschel Akiba Ainspan

Glen Arthur Wiedemeier

Ankur Agrawal

Carrie Ellen Cox

Eric John Lukes

Yong Liu

Michael B Spear

Guanghua Shu

An apparatus comprises one or more A-type resistance segments, wherein each A-type resistance segment comprises one or more A-type switches, at least one A-type linear resistor coupled to the one or more A-type switches, at least one A-type tunable header unit coupled to the one or more A-type switches, and at least one A-type tunable footer unit coupled to the one or more A-type switches; one or more B-type resistance segments, wherein each B-type resistance segment comprises one or more B-type switches, at least one B-type linear resistor coupled to at least a proper subset of the one or more B-type switches, at least one B-type tunable header unit coupled to the one or more B-type switches, and at least one B-type tunable footer unit coupled to the one or more B-type switches; and wherein second terminals of the A-type linear resistors and the B-type linear resistors are coupled together.

Segmented digital-to-analog converter wireline driver

A circuit includes at least three equally weighted drivers; a state variable generator; and an element selector. The latter is coupled to the drivers, has a first input from the generator, has a second input including a plurality of input thermometer-encoded data streams, and has an output of an equal number of thermometer-encoded output data streams supplied to the drivers. The element selector maps the second input to the output dynamically based on a value of the first input from the state variable generator, with an update rate that is no more than one half of a symbol-rate. A serializer is configured to provide serialized data at the symbol rate, with output coupled to one of the second input of the element selector and input of the drivers. The drivers have outputs that are combined to produce an output of the circuit at the symbol rate.

Transmitter with uniform driver segment activity

Aspects of the invention include receiving, by a controller, an indication of a chip initialization for a duty cycle correction (DCC) circuit, wherein the duty cycle correction circuit includes a main path including a main multiplexer (MUX) having a first input and a main driver circuit, a replica path including a replica MUX having a second input and a replica driver circuit, a selection MUX connected to the main path and the replica path, operating the selection MUX, during a period for the chip initialization, to select the main path as an input to the selection MUX, inputting a pre-defined data pattern to the main path, comparing an output of the selection MUX with the pre-defined data pattern to determine duty cycle issue, and generating an adjustment vector based on the determined duty cycle issue.

Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output

A serial transmitter that outputs one symbol every unit interval (UI) from a data source is presented. The serial transmitter includes a serial output port that outputs one symbol every unit interval (UI) from a data source. The serial transmitter also includes a plurality of driver segments that jointly drive the serial output port. Each driver segment is configured to use one of N phases of a sampling clock to serialize and transmit data from the data source. Different sets of the driver segments are configured to use different phases of the sampling clock for serializing and transmitting data, the sampling clock being a half-rate clock having a period of two UI.

Serial transmitter with feed forward equalizer

A four-level pulse amplitude modulation transmitter and corresponding method are provided. The transmitter includes a most significant bit processing section and a least significant bit processing section. The transmitter further includes at least one termination resistor connected to respective outputs of the processing sections to provide a transmitter output. Each of the processing sections include a set of retiming latches arranged in a parallel for aligning input parallel data and providing parallel aligned latched outputs responsive to one phase of a quarter-rate four-phase quadrature clock. Each of the processing sections further includes a serializer for serializing the parallel aligned latched outputs to provide a serialized output using quarter-rates of the quarter-rate four-phase quadrature clock. Each of the processing sections also include an output driver for driving the serialized output.

4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases

A method and system of equalizing in a decision feedback equalizer is provided. A plurality of adder circuits receives a digital code representing a previously decided symbol from an output of a prior path of a plurality of paths. A decision-making slicer circuit receives an input voltage and a first clock signal. The plurality of adder circuits receives a second clock signal and injects an offset current proportional to the digital code representing the previously decided symbol into a current injection input of the decision-making slicer circuit, at a first edge of the second clock signal. There is a predetermined skew between the first clock and the second clock to control a timing between the injection of the offset current of the plurality of adder circuits and the initiation of a decision-making phase of the decision-making slicer circuit.

High speed DFEs with direct feedback

A timing error detection circuit for calibrating a serial transmitter is disclosed. The circuit includes a data source configured to provide data for serial transmission and a clock source configured to produce N versions of a sampling clock that are at N different phases of the sampling clock. The detection circuit has a first sampler configured to sample the data source by using a first phase of the sampling clock to generate a first sampled signal and a second sampler configured to sample the data source by using a second phase of the sampling clock to generate a second sampled signal. The detection circuit also includes a first comparator configured to compare the first and second sampled signals to generate a difference signal and a first low-pass filter configured to filter the difference signal to generate an average difference voltage. A second comparator in the detection circuit is configured to compare the average difference voltage with a reference voltage.

Serial transmitter with feed forward equalizer and timing calibration

A four-level pulse amplitude modulation receiver has a four-level pulse amplitude modulation mode and a non-return-to-zero modulation mode. First, second, and third four-level pulse amplitude modulation samplers are coupled to an input. Each of the samplers has a corresponding output in turn including a corresponding binary decision of the first, second, and third samplers. A four-level pulse amplitude modulation decoder circuit has inputs coupled to the outputs of the samplers. The four-level pulse amplitude modulation decoder circuit is active in the four-level pulse amplitude modulation mode. The receiver also includes a non-return-to-zero majority voting circuit coupled to the outputs of the samplers. The non-return-to-zero majority voting circuit has an output and is configured to output a majority decision of the corresponding binary decisions of the samplers, and is active in the non-return-to-zero modulation mode.

Dual-mode non-return-to-zero (NRZ)/ four-level pulse amplitude modulation (PAM4) receiver with digitally enhanced NRZ sensitivity

A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

Efficient calibration of a low power parallel data communications channel

A parallel receiver interface includes a plurality of parallel data receivers, each receiver receiving input data. A clock receiver is configured to receive a forwarded clock. A phase interpolator has an input coupled to the output of the clock receiver and has an output coupled to each of the parallel receivers. Parallel clock delay elements are within each of the parallel data receivers, each clock delay element configured to provide varying amounts of clock phase adjustment. Inputs of a multiplexer circuit within each of the parallel data receivers are coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver. An output of the multiplexer circuit is coupled to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.

Power-scalable skew compensation in source-synchronous parallel interfaces

A communications parallel bus receiver interface having N data lines and method of operation. The parallel bus interface employs receiver redundancy at the bus level such that there are N+1 receiver devices. An input switching network is configured to receive and couple N parallel data signals along respective paths to corresponding parallel-configured bit receiver devices, and adapted to couple one received data signal to two adjacent bit receivers. A calibration device calibrates one of the two adjacent bit receivers, and a qualification device qualifies data decisions made during calibration processes performed by the calibration device. The method cycles through each of N+1 receivers to periodically recalibrate each receiver (one at a time) while N inputs are processed continuously and uninterrupted. The interface is configured such that another receiver is receiving the same data as the receiver that is being calibrated, and the qualifications for receiver calibration can be made with minimal circuit overhead.

Growing community of inventors

Danbury, CT, United States of America

Timothy O Dickson