International Business Machines Corporation

Timothy Michael Skergan

Ravi Kumar Arimilli

John Steven Dodson

Jerry Don Lewis

Kevin Franklin Reick

Thomas Pflueger

James Stephen Fields, Jr

Scott Barnett Swaney

Paul Frank Lecocq

Johnny James LeBlanc

Brian Chan Monwai

Michael Stephen Floyd

Asher Shlomo Lazarus

Joshua P Hernandez

Abel Alaniz

Daniel W Cervantes

Benjamin Robert Gass

William Vincent Huott

Steven Michael Douskey

Phillip John Restle

Roger Donell Weekly

Sungjun Chun

Jose Angel Paredes

Robert Louis Franch

Norman Karl James

Philip George Shephard, Iii

Robert Benjamin Gass

Roger Ned Bailey

James M Crafts

Neil R Vanderschaaf

Ching Lung Tong

Edward Michael Seymour

Tung Nang Pham

Timothy C Taylor

William B Maloney

Joseph E Dery

A method of calibrating a thermal sensor includes setting a wafer to a control temperature. The wafer includes the thermal sensor and other chip logic. The method also includes applying power exclusively to a thermal sensor circuit, calibrating the thermal sensor, and storing a calibration result. The method also includes retrieving the calibration result upon application of power to the other chip logic.

Calibration of an on-die thermal sensor

For disabling a first function in an information handling system, a dynamic signal is disabled. The first function is inoperable in response to the dynamic signal being disabled. At least a second function in the information handling system is operable irrespective of whether the dynamic signal is disabled.

Preventing circumvention of function disablement in an information handling system

Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.

Creating scan chain definition from high-level model using high-level model simulation

Illustrative embodiments disclose a data processing system providing low-level hardware access to in-band and out-of-band firmware. The data processing system includes a plurality of chips that includes at least one processor chip and a plurality of support chips. At least one processor chip includes a field replaceable unit support interface master that uses a field replaceable unit support interface serial transmission protocol to communicate with the plurality of support chips. Each one of the plurality of support chips includes a field replaceable unit support interface slave in, with ones of the plurality of chips that include a processor also include the field replaceable unit support interface master, and ones of the plurality of chips that do not include the processor include only the field replaceable unit support interface slave. Only the field replaceable unit support interface master possesses conversion logic.

Providing low-level hardware access to in-band and out-of-band firmware

A method for testing an electronic circuit comprises selecting a first log interval, a first log start pattern, a first log end pattern, and a first subset range of LBIST patterns from a plurality of LBIST patterns arranged in an order, wherein each LBIST pattern of the subset range of LBIST patterns causes an associated output of an electronic circuit. The method tests an electronic circuit in a first test by applying to the electronic circuit the first subset range of LBIST patterns sequentially in the order, thereby generating a first plurality of associated outputs. The method stores a first subset of associated outputs based on the first log interval, the first log start pattern, and the first log end pattern. The method compares the subset of associated outputs with known outputs to identify a first output mismatch.

Method and system for LBIST testing of an electronic circuit

A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor

A method for testing an electronic circuit comprises selecting a plurality of test patterns arranged in an order. The method tests an electronic circuit by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to a first log interval after the first test pattern, thereby generating a first associated output. The method compares the first associated output with a first known output of the plurality of known outputs. In the event the first associated output does not match the first known output, the method stores indicia of the first mismatch; causes the electronic circuit to appear to assume the first known output state; and proceeds with additional test procedures.

Method and system for testing an electronic circuit to identify multiple defects

A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., 'signature' of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.

Techniques for logic built-in self-test diagnostics of integrated circuit devices

An improved method and system for manipulation a plurality of graphical pointers utilizing a single graphical pointing device are disclosed. A plurality of graphical pointers are displayed within a display device. A user may then temporarily select one graphical pointer among the plurality of graphical pointers. During the selection, the selected graphical pointer is manipulated in response to operation of a single graphical pointing device. A point within the display device specified by the position of the selected graphical pointer is selected in response to closure of a switch associated with the selected graphical pointer.

Method and system for manipulating a plurality of graphical pointers

A method to reduce logic built in self test manufacturing test time of integrated circuits, comprising: loading a plurality of test seeds in bulk into a locally accessible on-chip memory array locally disposed on an integrated circuit, each of the plurality of test seeds is associated with a set of LBIST control information; sending the plurality of test seeds from the locally accessible on-chip memory array repetitively into a pseudo-random pattern generator one at a time during an LBIST operation being under the control from the set of LBIST control information; generating random bit streams serially into a plurality of parallel shift registers of the integrated circuit through the use of the plurality of test seeds; and performing a logic built-in self test on a plurality of logic blocks in the integrated circuit to detect defects within the integrated circuit.

System and method to reduce LBIST manufacturing test time of integrated circuits

In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

Method for providing low-level hardware access to in-band and out-of-band firmware

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e.g., 3 clock cycles worth of series connected inverters. Delay line taps (inverter outputs) are inputs to a register that is clocked by the complementary clock pair to capture progression of the launch clock through the delay line and identify any variation (e.g., from jitter, VDD noise) in that progression. Global clock skew and across chip gate length variation can be measured by cross coupling launch clocks from a pair of such clock buffers and selectively passing the local and remote launch clocks to the respective delay lines.

Built in self test circuit for measuring total timing uncertainty in a digital data path

A computer implemented method, testing system, computer usable program code, and apparatus are provided for measuring microprocessor susceptibility to internal noise A noise generator modulates a clock signal to generate noise on a targeted component within a microprocessor. A function generator executes microprocessor functions on a plurality of functional components within the microprocessor. A maximum execution frequency on the plurality of functional components is then measured and a set of frequency ranges where the functional components are susceptible to the generated noise is determined.

Measuring microprocessor susceptibility to internal noise generation

A method, computer program product and system for testing stuck-at-faults. A first register may be loaded with a first value where the first value may be written into each entry in a memory array. A second register may be loaded with a second value. A third register may be loaded with either the second value or a third value. The second and third values are pre-selected to test selector circuits for stuck-at-faults with a pattern where the pattern includes a set of bits to be inputted to selector circuits and a set of bits to be stored in the memory cells. A value stored in the n-most significant bits in both the second and third registers may be predecoded to produce a predecode value. The predecode value may be compared with the value stored in the n-most significant bits in an entry in the memory array to determine a stuck-at-fault.

Growing community of inventors

Austin, TX, United States of America

Timothy Michael Skergan