Lsi Logic Corporation

Timothy McGonagle

Todd A Randazzo

Jonathan Alois Schmitt

Kenneth G Richardson

Matthew Russell

Kenneth Stanley Szajda

Brad Wright

Gregory Shusta

A method and computer program for estimating a cell delay for an integrated circuit design include steps of selecting a range of values for cell ramptime and load and a range of values for an additional cell parameter. The values for cell ramptime, load, and the additional cell parameter are arranged in a lookup table. A cell delay is calculated for each combination of cell ramptime, load, and the additional cell parameter for the lookup table.

Device for estimating cell delay from a table with added voltage swing

An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.

Control circuit for power

Growing community of inventors

Fort Collins, CO, United States of America

Timothy McGonagle