International Business Machines Corporation

Timothy Mathew Philip

Kevin W Brew

Lawrence Alfred Clevenger

Injo Ok

Robert Russell Robison

Jin Ping Han

Youngseok Kim

Sagarika Mukesh

Nicole A Saulnier

Somnath Ghosh

Dominik Metzler

Alexander Reznicek

Soon-Cheon Seo

Ashim Dutta

John Christopher Arnold

Daniel James Dechene

Nicholas Anthony Lanzillo

Matthew Joseph BrightSky

Ching-Tzu Chen

Devendra K Sadana

Choonghyun Lee

Steven J Holmes

Chanro Park

Christopher J Penny

Abu Sebastian

Sanjay C Mehta

Muthumanickam Sankarapandian

Manuel Le Gallo-Bourdeau

Ghazi Sarwat Syed

Vara Sudananda Prasad Jonnalagadda

Benedikt J Kersting

Anirban Chandra

Caitlin Camille Stuckey

Rebecca Colby Martin

Steven M Mcdermott

A semiconductor component includes a dielectric layer including an opening. The semiconductor component further includes a liner arranged in the opening in direct contact with the dielectric layer. The semiconductor component further includes a wetting layer arranged in the opening in direct contact with the liner. The semiconductor component further includes an interconnect structure arranged in the opening in direct contact with the wetting layer. The semiconductor component further includes a cap arranged in the opening in direct contact with the interconnect structure and separated from the wetting layer by a spacer.

Damascene interconnect spacer to facilitate gap fill

A heater, a system, and a method for linearly changing the resistance of the phase change memory through a graded heater. The system may include a phase change memory. The phase change memory may include a dielectric. The phase change memory may also include a heater patterned on the dielectric, the heater including: an outside conductive heating layer that has a higher resistance than other layers of the heater, and an inside conductive heating layer that has a lower resistance than the outside conductive heating layer, where the outside conductive heating layer is at an outside area of the heater and the inside conductive heating layer is at an inside area of the heater. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Phase change memory with graded heater

A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.

Composite material phase change memory cell

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a 'horizontal' portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Phase change memory programming current leakage reduction

A computer memory device includes a bottom electrode, a top electrode, and a memory component arranged between the top electrode and the bottom electrode. The memory component is made of a dielectric solid-state material and is in direct contact with the top electrode and the bottom electrode. The computer memory device further includes a proximity heater configured to increase a temperature of a portion of the memory component. The computer memory device further includes a layer of dielectric material in direct contact with the proximity heater. The layer of dielectric material is in direct contact with one of the bottom electrode and the top electrode.

Proximity heater to lower RRAM forming voltage

A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Phase change memory cell with double active volume

Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Selective patterning of vias with hardmasks

An apparatus comprising a dielectric layer located between a first electrode and a second electrode and a third electrode located on the dielectric layer between the first electrode and the electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

Horizontal RRAM device and architecture for variability reduction

Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.

Insulated phase change memory using porous dielectrics

A phase change memory (PCM) cell comprises a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, a first phase change layer positioned between the first electrode and the second electrode and being comprised of a first phase change material, and a second phase change layer positioned between the first electrode and the second electrode and being comprised of a second phase change material. The first phase change material has a first resistivity, the second phase change material has a second resistivity, and wherein the first resistivity is at least two times the second resistivity.

Multi-layer phase change memory device

A phase change memory device is provided. The phase change memory device includes a phase change memory material within an electrically insulating wall, a first heater terminal in the electrically insulating wall, and two read terminals in the electrically insulating wall.

Multi-terminal phase change memory device

A non-volatile memory structure may include a phase change memory comprising a phase change material. The non-volatile memory structure may include a Schottky diode in series with the phase change memory, wherein a Schottky barrier of the Schottky diode is a surface of the phase change memory. This may be accomplished through a proper selection of materials for the contact of the phase change memory. This may create an integrated diode-memory structure which may control directionality of current without a penalty on the footprint of the structure.

Integrated diode memory device

An embodiment of the invention may include a semiconductor structure. The semiconductor structure may include a phase change element located above a heater. The heater may include a conductive element surrounding a dielectric element. The dielectric element may include an air gap.

Phase change memory

A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

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Albany, NY, United States of America

Timothy Mathew Philip