Intel Corporation

Timothy M Wilson

Songmin Kim

Tanay Karnik

Nasser A Kurd

Luiz M Franca-Neto

Praveen Mosalikanti

Greg F Taylor

Michael C Rifani

Bryan K Casper

James E Jaussi

Aaron K Martin

Gregory F Taylor

Navindra Navaratnam

Tanay Karnick

Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.

Method and apparatus for determining within-die and across-die variation of analog circuits

A method and apparatus for an integrated circuit having a offset reference circuit block to receive an external voltage reference and output an offset reference voltage are described herein.

On-die offset reference circuit block

A system and method for processing signals determines rise and fall times of a driving signal, compares the rise and fall times to desired values, and independently controls the rise and fall times to equal the desired values. The rise and fall times may be controlled by generating one or more first correction bits based on a difference between the rise time and a corresponding one of the desired values, generating one or more second correction bits based on a difference between the fall time and a corresponding one of the desired values, and then separately applying the bits to independently control the rise and fall times of the driving signal. The driving signal may be an I/O signal or another type of signal.

Closed-loop independent DLL-controlled rise/fall time control circuit

A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions. Two differential amplifier latches are employed, each with an evaluation phase on alternate transitions of a clock signal, so as to provide a higher throughput than if only one differential amplifier latch was employed.

CMOS Amplifier for optoelectronic receivers

A high bandwidth, single stage, low power cascode transimpedance amplifier for short haul optical links. In one embodiment, an input signal is fed into the source of a common-gate pMOSFET, the output signal is taken at the drain of the common-gate pMOSFET, and bias current is supplied by a pMOSFET and a nMOSFET biased in their triode regions.

High bandwidth, low power, single stage cascode transimpedance amplifier for short haul optical links

Growing community of inventors

Aloha, OR, United States of America

Timothy M Wilson