Sperry Corporation

Other

Vtc Inc.

Timothy M Lindenfelser

David A Hanson

A skew compensated RS422 buffer includes a skew compensation circuit and an output driver. The output driver is connected to receive a complementary pair of compensated drive signals, and provides complementary buffer output signals in response thereto. Due to asymmetric switching characteristics, buffer output signals in response to falling edge drive signals are delayed by an inherent skew period with respect to buffer output signals in response to rising edge drive signals. The skew compensation circuit includes a NOR gate and an AND gate, both of which have a first input terminal connected to receive buffer input signals. The buffer input signals are also applied to second input terminals of both the NOR gate and AND gate through delay gates which delay signal propagation by delay periods substantially equal to the inherent skew period of the output driver. A complementary pair of compensated drive signals are provided at output terminals of the NOR and AND gates, thereby compensating for the asymmetric switching characteristics of the output driver means.

Skew compensated RS422 buffer

A method for fabricating high performance bipolar transistors using a single polycrystalline silicon layer whereby horizontally and vertically scaled base/emitter junctions are achieved. In an extrinsic base transistor, a composite sandwich of overlying layers of poly silicon, oxide and nitride are deposited over a substrate containing field oxide isolated monocrystalline transistor sites having buried subcollectors and sinker regions. The composite sandwich is thereafter selectively oxidized to define base, emitter and collector regions with the relative thickness of the composite sandwich and the grown oxide being controlled to assure proper horizontal extrinsic base to emitter spacings and shallow vertical intrinsic base to emitter junctions, upon completing subsequent implant and annealing steps. Each active transistor site is also surrounded by a ring-like, channel stopper which is physically isolated from the channel stopper of each other device.

Single layer poly fabrication method and device with shallow

Improved silicon semi-conductor device and process includes three layer sandwich passivation coating. The sandwich coating comprises first, a thin silica layer, preferably produced by oxidizing a silicon surface to the minimum thickness necessary to prevent interdiffusion of an overlying nitride layer with the silicon subsurface. The second layer of the sandwich construction is nitride and the third layer is a thicker layer of silica, preferably produced by plasma glass deposition which, together with the inner silica layer provides preselected electrical characteristics required of the composite barrier or passivation coating. This invention reduces manufacturing defects produced in conventional two layer passivation coatings, including a thicker silica inner layer, due to undercutting of the thicker silica inner layer upon etching to form terminal areas. Such undercutting is avoided by the thin silica inner layer in the present invention.

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Eagan, MN, United States of America

Timothy M Lindenfelser