Exar Corporation

Timothy Lu

Vincent S Tso

Shin-Chung Chen

A low voltage CMOS output driver is adapted to generate an output voltage that stays within predefined limits at relatively low supply voltages. The output driver includes, in part, a voltage-controlled resistor, a voltage-controlled current sink, and a switching stage. A control circuit provides the voltages that are applied to the voltage-controlled resistor and the voltage-controlled current sink. The voltage applied to the voltage-controlled resistor defines the high output voltage. The voltage applied to the voltage-controlled current sink defines the low output voltage. The control circuit is a scaled replica of the output driver and is adapted to consume a current that is 1/L times the current consumed by the output driver.

Low power CMOS LVDS driver

A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180&#xb0; out-of-phase with respect to the third signal.

Method and apparatus to generate break before make signals for high speed TTL driver

A differential output driver includes an output block, a replication block, and a feedback control block. Each of the output and replication blocks further includes a preamplifier and a source-follower stage. The preamplifier of the output block receives a differential input voltage and generates a first differential voltage. The source-follower stage of the output block receives the first differential voltage and generates a differential output voltage. The preamplifier of the replication block receives first and second supply voltages and generates a second differential voltage. The source-follower stage of the output block receives the second differential voltage and generates a third differential voltage. The feedback control block receives the third differential voltage and generates a differential control voltage applied to the output block. The generated differential output voltage stays within predefined limits, such as those defined by the LvPECL standard.

CMOS LvPECL driver with output level control

A current mirror circuit that uses only a single seed current, and thus only a single current source. A transistor biasing circuit is connected in between the single current source and the two transistors of the first leg of the current mirror. The transistor biasing circuit provides two functions. First, the source current itself flows through the transistors of the transistor biasing circuit to the two transistors forming the first leg of the current mirror. Second, the transistor biasing circuit biases the gates of the transistors in the current mirror so that the output transistors are at the onset of saturation.

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Campbell, CA, United States of America

Timothy Lu