National Semiconductor Corporation

Timothy L Garverick

Ronald S Perloff

Hem P Takiar

Richard Dean Henderson

George F Reyling, Jr

Charles P Carinalli

James Sutherland

Farid A Yazdy

Webster B Meier

A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel. This has the effect of producing a three dimensional interconnect network from a two dimensional arrangement of arrays or chips in a MCM package. The result is a high gate capacity logic device having an increased degree of gate utilization and shortened average interconnect distances, thereby enabling the production of complex devices which have a faster operating speed.

Logical three dimensional interconnections between integrated circuit

In an FDDI token ring network, a repeat filter that treats FDDI Set and Reset symbols occurring in a frame prior to an End Delimiter symbol as a violation and does not repeat these symbols onto the FDDI ring. In addition to the three states described in the FDDI repeat filter standard for a byte-wide implementation, a repeat filter in accordance with the present invention includes a fourth END state. The presence of this END state allows the REPEAT state to be restricted such that it treats bytes within a frame with either symbol of the byte being either a Set or Reset symbol as a violation and a Halt byte is transmitted onto the ring; the repeat filter then enters the Halt state. In addition, the repeat filter is also responsive to 'mixed' bytes that consist of an FDDI data symbol and an FDDI control symbol. If the mixed byte is a data symbol followed by an End Delimiter symbol, then the repeat filter transmits an FDDI zero symbol followed by an End Delimiter symbol and enters the END state; if the mixed byte consists of a data symbol followed by an Idle symbol, then the repeat filter transmits an Idle byte and enters the Idle state.

Byte-wide repeat filter

Preamble smoothing for information character transmissions in a data transmission network is accomplished as follows. First, the smoothing filter identifies the start of a new preamble. If the start of a new preamble is identified and a previously received preamble has been extended, then the preamble is contacted by deleting an IDLE byte or, if the frame received prior to the initial IDLE byte was a frame fragment, then the information character preceding the initial IDLE byte is deleted. Following the contraction of the preamble, a determination is made as to whether next received byte is an IDLE byte. If it is not, then the preamble is extended by inserting an IDLE byte and the smoothing filter begins searching for the start of a new preamble. If it is, then a counter is incremented. If the counter has not yet reached its preset threshold, then the next byte is checked to determine whether it is an IDLE byte. If it is, then the counter is again incremented. This iterative process continues until the counter threshold is reached. At that point, the smoothing filter again begins searching for the start of a new preamble.

Smoothing filter

According to the present invention, each successive refresh to the multiple banks of a DRAM array is staggered by one clock period. Thus, the time required to refresh one row in each DRAM of each bank at 10 MHz, for example, is equal to 0.7 .mu.sec., or 4.4% of the total allowable maximum time between refresh cycles. This staggered refresh technique avoids large power supply current spikes while minimizing the effect on memory access bandwidth.

Staggered refresh for dram array

A three state inverter driver is operated so that its output goes to a logic one briefly just prior to going to its high impedance state when commanded by a disable pulse. This characteristic is useful where a plurality of drivers are employed to operate a DRAM element.

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Cupertino, CA, United States of America

Timothy L Garverick