Zilog, Inc.

Ixys Ch Gmbh

Timothy K Carns

Michael J Westphal

Lee J DeBruler

John L Horvath

John A Smythe

Brett D Lowe

John Eugene Berg

John A Ransom

Bernice L Kickel

Sungkwon Lee

A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer that is later etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

Method of fabricating high-performance capacitors in integrated MOS technologies

Process to improve high-performance capacitors in integrated MOS technologies

A method of fabricating a high performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used. In the preferred embodiment, this is of the Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) type, although other Anti-Reflective Coatings (ARCs) or layers, such as a conductive film like TiN may be employed. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. In one embodiment, a Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition. Another embodiment instead eliminates the capacitor dielectric removal step, which is then replaced by a step to form an additional layer which, in a second step, is then etched away to leave spacers on the capacitor sides, thereby eliminating any undercutting of the dielectric.

Process to improve high performance capacitor properties in integrated MOS technology

Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

Non-oxidizing spacer densification method for manufacturing semiconductor devices

A method for manufacturing a semiconductor device in which ROM programming ion implantation is performed by utilizing the same mask as used for implanting dopant in MOS transistors. The ROM programming ion implantation is conducted under the same conditions as the MOS transistor forming step. Only a single mask needs to be modified for the programming, thus reducing cost and complexity of manufacturing the device.

Method of forming semiconductor memory device with LDD

The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.

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Meridian, ID, United States of America

Timothy K Carns