International Business Machines Corporation

Infineon Technologies Ag

Globalfoundries Inc.

Other

Timothy Joseph Dalton

Lawrence Alfred Clevenger

Chih-Chao Yang

Carl John Radens

Anthony K Stamper

Jeffrey P Gambino

Sampath Purushothaman

Daniel C Edelstein

Kerry Bernstein

Keith Kwong Hon Wong

Louis C Hsu

Mark David Jaffe

Andrew Herbert Simon

Louis L Hsu

Matthew Earl Colburn

John Anthony Fitzsimmons

Ebenezer E Eshun

Kaushik Arun Kumar

Stephen McConnell Gates

Elbert Emin Huang

Paul David Kartschoke

Satyanarayana Venkata Nitta

Kevin Shawn Petrarca

Richard Paul Volant

Nicholas C M Fuller

Vincent James McGahay

Kangguo Cheng

Christopher Vincent Jahnes

Thomas M Shaw

Erdem Kaltalioglu

Chandrasekhar Narayan

Stephen Ellinwood Luce

Michael C Gaidis

Anil Kumar Chinthakindi

Katherine Lynn Saenger

Charles Thomas Black

Yun-Yu Wang

Edward Crandal Cooney, Iii

Jeffrey Curtis Hedrick

Mahadevaiyer Krishnan

Bruce Bennett Doris

Douglas Duane Coolbaugh

Kwong Hon Wong

Shyng-Tsong Chen

Katherina E Babich

Theodorus E Standaert

Ying Di Zhang

Sandra Guy Malhotra

Edmund Juris Sprogis

Peter Anthony Sandon

Ramachandra Divakaruni

Haining S Yang

Mukta G Farooq

Dirk Pfeiffer

Terry Allen Spooner

John Kenneth DeBrosse

George Frederick Walker

Stephen Edward Greco

Vidhya Ramachandran

James J Demarest

Clement Hsingjen Wann

Kevin K Chan

Alfred Grill

Timothy Harrison Daubenspeck

Wolfgang Sauter

Zhong-Xiang He

Christopher David Muzzy

Kenneth Parker Rodbell

Eugene John O'Sullivan

Wai-Kin Li

Louis Lu-Chen Hsu

Conal Eugene Murray

Donald Francis Canaperi

David Lee Rath

Wesley Charles Natzle

Carlos Juan Sambucetti

Robert Allen Groves

Ho-Cheol Kim

James L Speidell

Michael F Lofaro

Kenneth Jay Stein

Jack Allan Mandelman

Cyril Cabral, Jr

Soon-Cheon Seo

Hariklia Deligianni

Richard Stephan Wise

Roy Rongqing Yu

Ramachandran Muralidhar

Sufi Zafar

Stephen Mark Rossnagel

Richard Quimby Williams

Emanuel Israel Cooper

Naftali Eliahu Lustig

Paul Charles Jamison

John Christopher Arnold

William Joseph Murphy

Cornelia K Tsang

Kaushik Chanda

Panayotis Constantinou Andricacos

Scott David Halle

An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.

Photovoltaic module with a controllable infrared protection layer

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.

Methods and structures for protecting one area while processing another area on a chip

A sensing device includes a substrate having a source region and a drain region formed therein. A gate structure is formed over the substrate and includes a gate dielectric and a gate conductor. The gate conductor is formed on the gate dielectric and disposed between the source region and the drain region. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. A gate extension is formed in contact with or as part of the gate conductor and including a conductive material covering one or more surfaces of the well.

Extended gate sensor for pH sensing

Dielectric composite structures comprising interfaces possessing nanometer scale corrugated interfaces in interconnect stack provide enhances adhesion strength and interfacial fracture toughness. Composite structures further comprising corrugated adhesion promoter layers to further increase intrinsic interfacial adhesion are also described. Methods to form the nanometer scale corrugated interfaces for enabling these structures using self assembling polymer systems and pattern transfer process are also described.

Corrugated interfaces for multilayered interconnects

Various embodiments include semiconductor structures. In one embodiment, the semiconductor structure includes a chip having a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Forming semiconductor chip connections

Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape.

Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

Interconnect structures and design structures for a radiofrequency integrated circuit

A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.

Two-dimensional patterning employing self-assembled material

A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Double-sided integrated circuit chips

Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

Electrical fuses and resistors having sublithographic dimensions

Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Methods of fabricating passive element without planarizing and related semiconductor device

In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing &#x2153; of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.

Pattern formation employing self-assembled material

Growing community of inventors

Ridgefield, CT, United States of America

Timothy Joseph Dalton