International Business Machines Corporation

Timothy John Slegel

Dan F Greiner

Christian Jacobi

Michael K Gschwind

Chung-Lung K Shum

Eric M Schwarz

Jonathan D Bradbury

Fadi Y Busaba

Lisa Cranton Heller

Valentina Salapura

Mark S Farrell

Damian Leo Osisek

Charles W Gainey, Jr

Marcel Mitran

Donald W Schmidt

Anthony Saporito

Maged M Michael

Charles Franklin Webb

Erwin F Pfeffer

Harold Wade Cain, Iii

Jeffrey Paul Kubala

Bruce C Giamei

Khary J Alexander

Reid T Copeland

Gustav E Sittmann, Iii

Steven R Carlough

Ute Gaertner

Martin Recktenwald

Mark Anthony Check

Michael Billeci

James J Bonanno

Brenton F Belmar

Alper Buyuktosunoglu

Pradip Bose

Christopher A Krygowski

Christian Zoellin

Jonathan T Hsieh

Kenneth E Plambeck

Aditya Nitin Puranik

Matthias Klein

Pak-kin Mak

Ulrich Mayer

John G Rell, Jr

Peter Jeremy Relson

Jennifer A Navarro

Cedric Lichtenau

Elpida Tzortzatos

Michael Klein

John Stephen Liptay

James H Mulder

Robert R Rogers

Silvia Melitta Mueller

Anthony Thomas Sofia

Aaron Tsai

Frank Siegfried Lehnert

Michel H T Hack

Petra Leber

Barry Watson Krumm

Brian Robert Prasky

William Vincent Huott

Giora Biran

Tamas Visegrady

Ali Y Duale

Adam B Collura

Craig Raymond Walters

Kevin Alexander Stoodley

Scott Barnett Swaney

Bernd Nerz

Kerstin Claudia Schelm

Tin-Chee Lo

Klaus J Getzlaff

Christian Borntraeger

Dean G Bair

Ronald M Smith

Pradip Patel

Younes Manton

Giles R Frazier

Reinhard Theodor Buendgen

Brian David Barrick

Yuen H Chan

Gregory William Alexander

Peter Kenneth Szwed

Michael Andrew Blake

Louis P Gomes

Hans-Werner Tast

Jane Helen Bartik

Garrett M Drapala

Ashutosh Misra

Girish Gopala Kurup

David S Hutton

Patrick M West, Jr

John Robert Ehrman

Edward Thomas Malley

Stefan Payer

Kai Oliver Weber

Gerrit Koch

Andreas Wagner

Brian B Moore

Deanna P Berger

James Raymond Cuffney

Methods, system, and computer program product are disclosed for enhanced system level testing of an AI hardware accelerator comprising Artificial Intelligence (AI) primitives. The system level testing provides uncompromised test coverage of the AI hardware accelerator while enabling efficient and effective testing performance. Enhanced test data generation, result prediction, and test execution are provided for system level testing of AI hardware accelerator including the AI primitives.

System level testing of artificial intelligence primitives

An instruction to perform validity testing of a source value is executed. The executing the instruction includes obtaining the source value using at least one field of the instruction and obtaining a plurality of test controls using a field of the instruction. The one or more test controls of the plurality of test controls are used to specify which digit positions of the source value are to be tested for validity and what codes are valid codes for the digit positions specified to be tested. Validity testing of at least a portion of the source value is performed based on the plurality of test controls obtained using the field of the instruction, and the performing the validity testing provides a result. The result is provided for use in further processing.

Vector test decimal instruction for validity testing

A single architected instruction to perform multiple functions is executed. The executing includes performing a first function of the multiple functions and a second function of the multiple functions. The first function includes moving a block of data from one location to another location, and the second function includes setting one portion of a storage key using one selected key and another portion of the storage key using another selected key. The storage key is associated with the block of data and controls access to the block of data. The first function and the second function are performed as part of the single architected instruction.

Move data and set storage key based on key function control

Storage accesses for merge operations are minimized. A plurality of records of a plurality of input lists are merged. The merging includes determining that an input list of the plurality of input lists has become empty, and checking, based on determining that the input list has become empty, a control specific for the input list. The control is used to determine how to proceed, such as whether to end merging or continue merging.

Controlling storage accesses for merge operations

A conversion operation is performed which includes a plurality of conversion actions. A conversion action includes processing an instruction to convert selected data from a source data type to a target data type. The processing includes determining whether a data type indicated using the instruction is a valid data type for a select machine. The data type is a selected data type selected from the source data type or the target data type. The selected data is converted from the source data type to the target data type, based on determining that the data type is a valid data type for the select machine. An indicator is set to a select value to indicate the data type is an invalid data type, based on determining that the data type is an invalid data type for the select machine. The indicator is checked at an end of the conversion operation.

Detection of invalid machine-specific data types during data conversion

An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

Reset dynamic address translation protection instruction

Instruction processing is performed for an instruction. The instruction is configured to perform a function, which is to be performed in a plurality of processing phases. A processing phase is defined to store up to a selected amount of data. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of the function. Based on determining that the store into the designated area occurred, an interrupt is presented.

Program event recording storage alteration processing for a neural network accelerator instruction

A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Clock comparator sign control

In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor

An exception summary is provided for an invalid value detected during instruction execution. An indication that a value determined to be invalid was included in input data to a computation of one or more computations or in output data resulting from the one or more computations is obtained. The value is determined to be invalid due to one exception of a plurality of exceptions. Based on obtaining the indication that the value is determined to be invalid, a summary indicator is set. The summary indicator represents the plurality of exceptions collectively.

Exception summary for invalid values detected during instruction execution

Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.

An instruction is executed to perform a query function. The executing includes obtaining information relating to a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.

Instruction to query for model-dependent information

A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

Neural network processing assist instruction

Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Operating system deactivation of storage block write protection absent quiescing of processors

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Staatsburg, NY, United States of America

Timothy John Slegel