International Business Machines Corporation

Timothy John Mullins

Harold F Kossman

Jeffrey Powers Bradford

Jeffrey S McAllister

Nelson Ramirez

Richard James Eickemeyer

Charles J Archer

Brian E Smith

Joseph D Ratterman

Bruce Marshall Walk

Armando Manduca

Jeffrey Douglas Brown

Timothy Hume Heil

Charles Luther Johnson

Steven R Kunkel

Michael Joseph Corrigan

David Glenn Carlson

Michael Steven Faunce

Albert Sidelnik

Michael James McDermott

Travis Michael Drucker

James Allen Rose

Glen Warren Nelson

Joseph James Cahill

Ross Evan Johnson

David S Lake

Thomas Richard Crowley

Bruce Ralph Petz

Patrick James Christenson

Russell Paul VanDuine

Steven D Lewis

Mark A Bransford

An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

Context switch data prefetching in multithreaded computer

Systems, methods and articles of manufacture are disclosed for transposing array data on a SIMD multi-core processor architecture. A matrix in a SIMD format may be received. The matrix may comprise a SIMD conversion of a matrix M in a conventional data format. A mapping may be defined from each element of the matrix to an element of a SIMD conversion of a transpose of matrix M. A SIMD-transposed matrix T may be generated based on matrix M and the defined mapping. A row-wise algorithm may be applied to T, without modification, to operate on columns of matrix M.

Transposing array data on SIMD multi-core processor architectures

Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures.

Processing array data on SIMD multi-core processor architectures

Systems, methods and articles of manufacture are disclosed for compensating for motion of a subject during an MRI scan of the subject. k-space data may be received from the MRI scan of the subject. A first graphical image may be generated from a first set of data elements from the k-space data. Similarly, a second graphical image may be generated from a second set of data elements from the k-space data. An offset in pixels may be determined by which to translate the second graphical image from the first graphical image to compensate for the motion. The k-space data may be modified at a sub-pixel offset relative to the determined offset. A motion-compensated graphical image of the subject may be generated from the modified k-space data. Doing so reduces the search space evaluated to sharpen images generated from the k-space data.

Correcting subject motion in multiple resolutions in magnetic resonance imaging

An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations corresponding predetermined operational modes. A first BHT configuration is provided. Checking is provided to identify improved performance with another BHT configuration. The BHT is reconfigured to provide improved performance based upon the current workload.

Implementing polymorphic branch history table reconfiguration

A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which to perform diagnostics, an algorithm for the processing element to execute, a data set for the algorithm to execute against, a diagnostic function for the processing element to execute, a condition for executing the diagnostic function, and visualization parameters for memory local to the processing element. As a result, runtime diagnostics can be performed with sufficient degree of control and customization to aid debugging in a hierarchical parallel environment.

Distributed runtime diagnostics in hierarchical parallel environments

Embodiments of the invention provide a method, system and article of manufacture for parallel application load balancing and distributed work management. In one embodiment, a hierarchy of master nodes may be used to coordinate the actions of pools of worker nodes. Further, the activity of the master nodes may be controlled by a 'coordinator' node. A coordinator node may be configured to distribute work unit descriptions to the collection of master nodes. If needed, embodiments of the invention may be scaled to deeper hierarchies.

Parallel computing system using coordinator and master nodes for load balancing and distributing work

An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of at least one instruction likely to be executed by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, one or more instructions may be prefetched on behalf of that thread so that when execution of the thread is resumed, those instructions are more likely to be cached, or at least in the process of being retrieved into cache memory, thus enabling a thread to begin executing instructions more quickly than if the thread was required to fetch those instructions upon resumption of its execution.

Context switch instruction prefetching in multithreaded computer

A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. Each stored thread state includes predefined selection data. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, uses the stored predefined selection data for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.

Method and apparatus for implementing thread replacement for optimal performance in a two-tiered multithreading structure

A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold value. Next thread selection logic coupled between the first tier thread state storage and a currently executing processor state, picks a next thread to run on a processor from the limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, selectively exchanges thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.

Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate

Method and apparatus for managing data on DASD units to improve system performance comprises monitoring portions of data on a plurality of DASD units to determine the times the data is accessed within a given time period, and characterizing accessed data portions of a DASD unit as HOT and COLD data. The DASD units are monitored to determine the number of times each unit is accessed within a time period to develop utilization factors reflective of the number of times the DASD unit is accessed during the time period. HOT and COLD data is moved between DASD units based on the utilization factors of the DASD units.

Dynamic DASD data management and partitioning based on access frequency utilization and capacity

A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected point within the first thread is stored, execution of the first thread is terminated and a second thread is selected for execution only in response to a level two or higher cache miss, thereby minimizing processor delays due to memory latency. The validity state of each thread is preferably maintained in order to minimize the likelihood of returning to a prior thread for execution before the cache miss has been corrected. A least recently executed thread is preferably selected for execution in the event of a nonvalidity indication in association with all remaining threads, in anticipation of a change to the valid status of that thread prior to all other threads. A thread switch bit may also be utilized to selectively inhibit thread switching where execution of a particular thread is deemed necessary.

Method and system for multi-thread switching only when a cache miss

An integrated semiconductor VLSI chip design that increases the number of driver circuits, or groups of driver circuits, that can be simultaneously switched. Timed driver gating signals, or driver enable signals, are used, in conjunction with physical grouping of driver circuits on the chip, to isolate switching drivers from quiet drivers. This construction and arrangement minimizes detrimental effects usually caused by noise that is generated when driver circuits switch.

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Rochester, MN, United States of America

Timothy John Mullins