Apple Inc.

Microsoft Technology Licensing, LLC

Brocade Communications Systems, Inc.

Silicon Graphics, Incorporated

Brocade Communication Systems LLC

Silicon Grahphics, Inc.

Timothy John Millet

Manu Gulati

Michael F Culbert

Erik P Machnicki

Joseph P Bratt

Jung Wook Cho

Brijesh Tripathi

Guy Cote

James B Keller

James Han Wang

Zongjian Chen

Zahid S Hussain

Gilbert H Herbeck

Joshua P De Cesare

Shane J Keil

Shun Wai Go

Anand Dalal

Joseph J Cheng

Peter F Holland

David Gerard Conroy

Josh P De Cesare

Suk Hwan Lim

D Amnon Silverstein

Ting Chen

Bin Ni

Shing Horng Choo

Jim Chen Chou

Stephan Vincent Schell

Mark P Rygh

Surya Parkash Varanasi

Jun Zhai

Binu K Mathew

John Bruno

Alexei Elias Kosut

Haitao Guo

Gurjeet S Saund

Arthur L Spence

Toshinari Takayanagi

Kung-Ling Ko

Girault W Jones

Robert P Esser

Toshi Takayanagi

Sally Fung

Alexandros Michael Tourapis

David William Singer

Keith Alan Cox

William C Athas

Sukalpa Biswas

Cyril De La Cropte De Chanterac

Barry J Corlett

Conrad Sauerwald

Kleanthes G Koniaris

Jeffrey E Frederiksen

Deniz Balkan

Marc A Schaub

Conrad Havluj Ziesler

Craig M Okruhlica

Weichun Ku

Raman S Thiara

Weihua Mao

Nitin Bhargava

Muditha Kanchana

Shailendra S Desai

James E Orr

Vijay Gupta

Manching Ko

Gaurav S Gulati

Shing I Kong

Shun Wai (“Dominic”) Go

Indraneel Ghosh

James Wang

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

System on a chip with always-on processor

In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Always-on audio control for mobile device

In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.

System on a chip with always-on component with powered-down configurations to process audio samples

In an embodiment, an electronic device may be configured to capture still frames during video capture but may capture the still frames in the 4&#xd7;3 aspect ratio and at higher resolution than the 16&#xd7;9 aspect ratio video frames. The device may interleave high resolution, 4&#xd7;3 frames and lower resolution 16&#xd7;9 frames in the video sequence, and may capture the nearest higher resolution, 4&#xd7;3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16&#xd7;9 frames in the video sequence, and then expand to 4&#xd7;3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16&#xd7;9 video frames responsive to a release of the shutter button.

Modeless video and still frame capture

In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Combined transparent/non-transparent cache

A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

Video encoder with context switching

A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.

Package with SoC and integrated memory

Growing community of inventors

Mountain View, CA, United States of America

Timothy John Millet