Broadcom Corporation

Broadcom Europe Limited

Alphamosaic Limited

Timothy James Ramsdale

Stephen John Barlow

David Plowman

Robert Swann

Neil Bailey

Martin Whitfield

Nel Bailey

An integrated circuit supports auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength.

Drive strength adjustment through voltage auto-sense

A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.

Register file with separate registers for compiler code and low level code

Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed and may include generating at least one control signal that controls a plurality of directional modes of at least one contact pad on a mobile multimedia processor (MMP) in an integrated circuit. Selectable modes may include: bidirectional, input, and an output mode. Each of the modes includes a bypass mode and a processing mode that may be controlled by the generated control signal. Received data may be processed by circuitry in the MMP when the processing mode may be enabled. Received data may be passed through the MMP without being processed by the MMP when the bypass mode may be enabled. An additional signal may be generated to dynamically pull-down a potential of the at least one contact pad and/or to pull-up a potential of said at least one contact pad.

System method for I/O pads in mobile multimedia processor (MMP) that has bypass mode wherein data is passed through without being processed by MMP

Certain embodiments of the invention may be found in a method for integrated circuit supporting auto-sense of voltage for drive strength adjustment. The method may comprise detecting an input voltage received at an auto-sense pad integrated on a mobile multimedia processing (MMP) chip. The input voltage may be a power supply voltage of the peripheral device received during power-up of the MMP chip, power-up of the peripheral circuitry, and/or dynamically while the MMP is powered-up. The auto-sense pad may adjust drive strength of at least one other pad, which may be an output pad or a bidirectional pad, integrated on the MMP chip may be configured to operate using the determined output voltage. A rise time and/or fall time of signals output by the MMP chip may be varied by the adjustment of the drive strength.

Method and system for an integrated circuit supporting auto-sense of voltage for drive strength adjustment

Methods and systems for input/output pads in a mobile multimedia processor are disclosed and may include receiving data from a host device in an integrated circuit having at least one contact pad and generating at least one control signal that controls the contact pads. The received data may be processed by the MMP based on the generated at least one control signal, or may be passed through the MMP in a bypass mode based on the control signal, thereby allowing the received data to pass through the MMP without processing to an external memory via the at least one contact pad, thereby sharing the external memory with the host device. The data may be transferred to external memory coupled to a contact pad on the MMP when the received data is to be passed through the MMP. The received data may be stored temporarily before transfer to an external device.

A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.

Vector processing system

In a multimedia system, a method and system for deglitching in a mobile multimedia processor are provided. A deglitching operation may be provided to reduce noise and compensate for strobe signal delays that may result in false bus cycles and other operating errors. A circuit comprising a plurality of delay cells, a multiplexer, and a latch may be utilized to perform the deglitching operation. The delay cells may be selected from several delay options having different time delays based on operating temperature and applied supply voltage. The time delay may be programmable and may be dynamically varied in accordance with the operation of the mobile multimedia processor.

Method and system for deglitching in a mobile multimedia processor

In a multimedia system, a method and system for input/output pads in a mobile multimedia processor are provided. Input, output, and/or bidirectional pads in a host bus interface and/or a slave bus interface may be configured to provide bypass capabilities when a mobile multimedia processor is powered down or hibernating. The pads may be adapted to provide pull-up and pull-down capabilities. The pull-up and pull-down capabilities may be dynamically programmed.

A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and to implement the defined operation on said value pair to generate a respective result; and a scalar result unit for receiving the results of the parallel processing units and for using said results in a manner defined by the scalar modifier to generate a single output value for said instruction.

Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction

A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

Narrow/wide cache

A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first group of cells all of which are located in the same column but in different rows.

Two dimensional data access in a processor

Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction

Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the register memory. The plurality of operands may be one or more contiguous regions. The contiguous regions may be specified as an address and a format such as a row, a column, or a neighborhood relative to the address.

Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file

A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.

Growing community of inventors

Cambridge, United Kingdom

Timothy James Ramsdale