Hitachi Global Storage Technologies Netherlands B.v.

Sandisk 3d LLC

International Business Machines Corporation

Sandisk Technologies Inc.

Timothy James Minvielle

Tong Zhang

Wipul Jayasekara

Howard Gordon Zolla

Jeffrey Scott Lille

Yung-Tin Chen

Ying Hong

Douglas Johnson Werner

Satoru Araki

Robert Beach

Linden James Crawforth

Chu-Chen Fu

Thomas L Leong

Shawn Marie Collier Hernandez

Benjamin Lu Chen Wang

Benjamin L Wang

A phase change memory device containing a phase change memory material layer includes a vertically repeating sequence of unit layer stacks located over a substrate, a plurality of openings vertically extending through the vertically repeating sequence, a plurality of vertical bit lines located within a respective one of the plurality of openings, and vertical stacks of insulating spacers. Each of the unit layer stacks includes an insulating layer, at least one of the phase change memory material layer or a threshold switch material layer, and an electrically conductive word line layer. Each of the insulating spacers laterally surrounds a respective one of the plurality of vertical bit lines, and contacts a sidewall of a respective one of the electrically conductive word line layers.

Three-dimensional phase change memory arrays and methods of manufacturing the same

A fabrication process for a resistance-switching memory cell uses metal oxide as a resistance-switching material. A metal oxide film having an initial stoichiometry is deposited on an electrode using atomic layer deposition. A changed stoichiometry is provided for a portion of the metal oxide film using a plasma reduction process, separate from the atomic layer deposition, and another electrode is formed adjacent to the changed stoichiometry portion. The film deposition and the plasma reduction can be performed in separate chambers where conditions such as temperature are optimized. The metal oxide film may be deposited on a vertical sidewall in a vertical bit linememory device. Optionally, the mean free path of hydrogen ions during the plasma reduction process is adjusted to increase the uniformity of the vertical metal oxide film. The adjustment can involve factors such as RF power, pressure and a bias of the wafer.

Plasma reduction method for modifying metal oxide stoichiometry in ReRAM

A memory cell including a first electrode, a second electrode and a first resistance-switching layer located between the first and second electrodes. The first resistance-switching layer comprises hafnium silicon oxynitride.

Composition of memory cell with resistance-switching layers

A method is disclosed for fabricating a CPP read head for a magnetic disk drive having an electrical isolation layer. The method includes providing a first shield layer, depositing a sensor stack on the first shield layer, a CMP stop layer is deposited on the sensor stack, and a release layer is deposited a on the CMP stop layer. Photoresist material containing Si is deposited on the release layer, and the photoresist material is then patterned and then oxidized by Reactive Ion Etching to form a high temperature photomask. The electrical isolation layer is then deposited to surround the sensor stack using a high temperature deposition process. The read head is then continued as either an in-stack bias sensor with 'draped shield' variation, or a hard bias stabilization variation.

CPP read sensor fabrication using heat resistant photomask

A method is presented for fabricating a read head having a read head sensor and a hard bias/lead layer which includes depositing a strip of sensor material in a sensor material region, and depositing strips of fast-milling dielectric material in first and second fast-milling dielectric material regions adjacent to the sensor material region. A protective layer and a layer of masking material is deposited on the strip of sensor material and the strips of fast-milling dielectric material to provide masked areas and exposed areas. A shaping source, such as an ion milling source, is provided which shapes the exposed areas. Hard bias/lead material is then deposited on the regions of sensor material and fast-milling dielectric material to form first and second leads and a cap on each of these regions. The cap of hard bias/lead material and the masking material is then removed from each of these regions.

Method to improve ability to perform CMP-assisted liftoff for trackwidth definition

An onboard electronic lapping guide for lapping a magneto-resistive head having a magneto-resistive sensor element disposed for electrical communication with a pair of sensor electrical leads. The lapping guide includes an electronic lapping guide resistive element disposed for electrical communication with the sensor electrical leads. The resistive element has a predetermined height in a lapping direction and is adapted to produce an electrical resistance in the presence of a lapping current that increases as said resistive element height is reduced during lapping. A lapping method and a method of forming the onboard electronic lapping guide are also disclosed.

Onboard multiphase electronic lapping guide design for MR heads

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San Jose, CA, United States of America

Timothy James Minvielle