International Business Machines Corporation

Timothy J Von Reyn

Gerard M Salem

R Dean Adams

Gary William Maier

Jay Gerald Heaslip

A BIST system that utilizes ECC to correct single bit errors in a given memory word at a given address, the ECC having a maximum number of bit errors it can correct in the given memory word. A first set of gates is coupled to an array of memory cells that stores a plurality of memory words, each at a given address. The first set of gates provides bit outputs indicative of errors in a given memory word while the given memory word is under test. A circuit coupled to respective outputs of the first set of gates determines if a number of errors in the memory word under test exceeds the maximum number of errors correctable by the ECC.

Testing of ECC memories

A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.

Optimized ECC/redundancy fault recovery

A structure and method for an integrated circuit which includes read/write memory having a plurality of memory devices, each of the memory devices having a unique address; a built-in self-test (BIST) engine, the BIST engine having a controller responsive to a test enable signal and operative to generate and store test data in the read/write memory; a comparator operative to compare retrieved data read from the read/write memory and the test data during a first pass test, the comparator identifying failed cycles where the retrieved data does not correspond correctly to the test data; and a diagnostic unit operative to store the failed cycles and being responsive to the controller generating and storing the test data in the read/write memory and operative to store failed data and failing addresses during a first pass test, wherein the BIST engine stops only at each of the failed cycles during the first pass test.

Growing community of inventors

Williston, VT, United States of America

Timothy J Von Reyn