Nintendo Co., Ltd.

Silicon Graphics, Incorporated

Mips Technologies, Inc.

Sun Microsystems, Inc.

Ati Technologies Inc.

Other

Ati Technologies Ulc

Artx

Timothy J Van Hook

Howard H Cheng

Farhad Fouladi

Robert J Moore

Anthony P DeLaurier

Henry Packard Moreton

William A Huffman

Earl A Killian

Carroll Philip Gossett

Genyo Takeda

Shuhei Kato

Nathan F Pooley

Harold S Anderson

Stephen J Shepard

Jeffrey C Doughty

Byron Sheppard

John Princen

Mark M Leather

Peter Y Hsu

Robert Yung

Robert A Drebin

Leslie Dean Kohn

Peter Anthony Sandon

Yu-Chung C Liao

Gulbin Ezer

Patrick Y Law

Matthew Komsthoeft

Gordon Elder, Iii

Sudhaker Rao

Leslie D Kohn

Gregory H Efland

Stephen C Fenwick

Michael L Fuccio

Walter E Donovan

Robert S Mace

Man Kit Tang

Ronald Nicholson

Charles F Tuffli, Iii

Peter Yan-Tek Hsu

Perter Hsu

Robert W Pryor, Jr

Carroll Phillip Gossett

The present invention provides a scheme for compressing the color components of image data, and in particular, data used in multi-sampled anti-aliasing applications. Adjacent pixels are grouped into rectangular tiles, with the sample colors stored in compressed formats accessible via an encoded pointer. In one embodiment, duplicate colors are stored once. Unlike prior compression schemes that rely on pixel to pixel correlation, the present invention takes advantages of the sample to sample correlation that exists within the pixels. A memory and graphics processor configuration incorporating the tile compression schemes is also provided. The configuration defines the tile sizes in main memory and cache memory. In one embodiment, graphics processor relies on a Tile Format Table (TFT) to process incoming tiles in compressed formats. The present invention reduces memory consumption and speeds up essential and oft-repeated operations in rendering. Thus it is valuable in the design and manufacture of graphic sub-systems.

Method and apparatus for compression of multi-sampled anti-aliasing color data

The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Providing extended precision in SIMD vector arithmetic operations

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics system has a graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. The embedded frame buffer is selectively configurable to store the following pixel formats: point sampled RGB color and depth, super-sampled RGB color and depth, and YUV (luma/chroma). Graphics commands are provided which enable the programmer to configure the embedded frame buffer for any of the pixel formats on a frame-by-frame basis.

Graphics system with embedded frame buffer having reconfigurable pixel formats

The present invention provides a scheme for compressing and decompressing the depth, or Z, components of image data. Image data is grouped into a plurality of tiles. A test is performed to determine if a tile can be compressed so that its size after compression is less than its size before compression. If so, the tile is compressed. A tile table includes a flag that can be set for each tile that is compressed. In one scheme, each tile comprises a 4&#xd7;4 block of pixels. For each pixel, the visible depth complexity is determined where each visible level of depth complexity is represented by a plane equation. Depending on the depth complexity, a compression scheme is chosen that stores multiple plane equations in cache lines. The compression scheme can be used with unsampled or multisampled data and provides higher levels of compression in multisampled environments.

Compression and decompression of data using plane equations

A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.

Method and apparatus for obtaining a scalar value directly from a vector register

The present invention provides for programmable interleaved graphics processing. The invention provides an execution pipeline and a number of registers. Each register holds instructions from a separate program. Instructions from the registers are interleaved in the execution pipeline such that the average latency is one instruction per cycle. This is accomplished even when there is conditional branching and execution latency. When one instruction has a dependency based on execution of a previous instruction, that second instruction is not provided to the execution pipeline until completion of the first instruction. However, in the meantime interleaved instructions from other programs are still being executed while the first instruction of the first program is executing. Thus the pipeline is always full and the processor is always working at peak capacity. The automatic interleaving of instructions permits simplified graphics software routines to be written. There is no need for the programmer or developer to anticipate or attempt to eliminate conditional branching or to worry about instruction latency. The design of the programmable interleaved graphics processing system provides a solution to those problems.

Method and apparatus for interleaved graphics processing

The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register. Then, a subset of elements are selected from the first register and the second register. The elements from the subset are then replicated into the elements in the third register in a particular order suitable for subsequent SIMD vector processing.

Alignment and ordering of vector elements for single instruction multiple data processing

Graphics system with embedded frame butter having reconfigurable pixel formats

A graphics processor includes an embedded frame buffer for storing frame data prior to sending the frame data to an external location, such as main memory. A copy pipeline is provided which converts the data from one format to another format prior to writing the data to the external location. The conversion may be from one RGB color format to another RGB color format, from one YUV format to another YUV format, from an RGB color format to a YUV color format, or from a YUV color format to an RGB color format. MPEG image data initially stored in main memory in a YUV format as a texture is transferred to the embedded frame buffer prior to initiating a copy-out process via the copy pipeline from the embedded frame buffer to an external frame buffer in main memory. During the copy-out process, pixels are converted from YUV format to an RGB format. A new texture image containing MPEG image data is placed in the embedded frame buffer prior to each successive copy out process operation so as to produce a streaming video image as a surface texture on at least a portion of a displayed object image.

Graphics system with copy out conversions between embedded frame buffer and main memory for producing a streaming video image as a texture on a displayed object image

A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The graphics pipeline renders and prepares images for display at least in part in response to polygon vertex attribute data and texel color data stored as a texture images in an associated memory. An efficient texturing pipeline arrangement achieves a relatively low chip-footprint by utilizing a single texture coordinate/data processing unit that interleaves the processing of logical direct and indirect texture coordinate data and a texture lookup data feedback path for 'recirculating' indirect texture lookup data retrieved from a single texture retrieval unit back to the texture coordinate/data processing unit. Versatile indirect texture referencing is achieved by using the same texture coordinate/data processing unit to transform the recirculated texture lookup data into offsets that may be added to the texture coordinates of a direct texture lookup. A generalized indirect texture API function is provided that supports defining at least four indirect texture referencing operations and allows for selectively associating one of at least eight different texture images with each indirect texture defined. Retrieved indirect texture lookup data is processed as multi-bit binary data triplets of three, four, five, or eight bits. The data triplets are multiplied by a 3&#xd7;2 texture coordinate offset matrix before being optionally combined with regular non-indirect coordinate data or coordinate data from a previous cycle/stage of processing. Values of the offset matrix elements are variable and may be dynamically defined for each cycle/stage using selected constants. Two additional variable matrix configurations are also defined containing element values obtained from current direct texture coordinates. Circuitry for optionally biasing and scaling retrieved texture data is also provided.

Method and apparatus for interleaved processing of direct and indirect texture coordinates in a graphics system

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Atherton, CA, United States of America

Timothy J Van Hook