Advanced Micro Devices Corporation

Spansion Llc.

Micron Technology Incorporated

Cypress Semiconductor Corporation

Other

Timothy J Thurgate

Daniel Sobek

Sameer S Haddad

Mark W Randolph

Kuo-Tung Chang

Carl Robert Huster

Srinivasa Banna

Richard M Fastow

Chi K Chang

Hiroyuki Kinoshita

Michael Allen Van Buskirk

Scott D Luning

Wei Zheng

Zhizheng Liu

Ashot Melik-Martirosian

Shenqing Fang

Yue-Song He

Vei-Han Chan

Mark T Ramsbey

Angela Tai Hui

Pau-Ling Chen

Hao Fang

Nicholas H Tripsas

Narbeh Derhacobian

Unsoon Kim

Shankar Sinha

Kuo Tung Chang

Scott Luning

Sung-Yong Chung

Gulzar Ahmed Kathawala

Janet S Wang

Nga-Ching Wong

Kazuhiro Mizutani

Tuan Duc Pham

Ning Cheng

Yi He

Xuguang Alan Wang

Chungho Lee

Ming-Sang Kwan

Sheung-Hee Park

Gabrielle Wing Han Leung

Bin Yu

Hiroyuki Ogawa

Yu Nan Sun

Darlene G Hamilton

Ravi S Sunkavalli

Olov B Karlsson

Suketu Arun Parikh

Chih-Yuh Yang

Emi Ishida

Youseok Suh

Rinji Sugino

Ming Sang Kwan

Jean Yee-Mei Yang

David Michael Rogers

Jihwan Choi

Masaaki Higashitani

Michael David Fliesler

Kyunghoon Min

Michael Brennan

Kelwin Ko

Ian Morgan

Narbeh Derhocobian

Yun Sun

Sugino Rinji

Paohua Kuo

Ngaching Wong

Michael A Van Bushkirk

Srinivasa Rao Banna

A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon ('poly') resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

Tilted implant for poly resistors

A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.

Charge-trapping memory device

Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.

Semiconductor memory device and method for biasing same

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

Techniques for providing a semiconductor memory device

Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns, each memory cell. Each of the memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a gate region and disposed between the first region and the second region, wherein the body region may include a plurality of floating body regions and a plurality of floating gate regions capacitively coupled to the at least one word line.

Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.

A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

Memory device protection layer

A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.

Method of forming an electronic device including forming a charge storage element in a trench of a workpiece

A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.

Apparatus and method for extended nitride layer in a flash memory

A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.

Memory device with buried bit line structure

A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures.

Semiconductor memory comprising dual charge storage nodes and methods for its fabrication

A memory device comprising an optimization component that facilitates erasing memory cells in a substantially homogeneous electromagnetic field and methods that facilitate erasing memory cells in a substantially homogeneous electromagnetic field are presented. The optimization component facilitates selecting a subset of memory cells to be erased at the same time, such that a memory cell in the subset of memory cells has two neighbor memory cells adjacent thereto that are in the subset of memory, or one neighbor memory cell adjacent thereto when the memory cell is an end-row memory cell. The optimization component facilitates performing a Fowler-Nordheim channel erase to erase the subset of memory cells, and a predetermined voltage potential associated with an erase command is applied to each cell of the subset of memory cells to facilitate reducing fringing effect associated with the electromagnetic fields applied to the cells during the erase.

Selective application of word line bias to minimize fringe effects in electromagnetic fields during erase of nonvolatile memory

The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back end processing.

Using thick spacer for bitline implant then remove

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Sunnyvale, CA, United States of America

Timothy J Thurgate