Altera Corporation

Calos Fund Limited Liability Company

Timothy J Southgate

Michael Phipps

Stephen J Smith

Michael V Wenzler

James G Schleicher

Alan Louis Herrmann

A method of loading data into register files that correspond to respective execution units within a data-parallel processor. After receiving a first set of parameters that specify a subset of data within a first memory, the first set of parameters are compared to a plurality of sets of conditions that correspond to respective patterns of data. The first set of parameters is then converted to a second set of parameters in accordance with one of the sets of conditions satisfied by the first set of parameters. A sequence of memory addresses are generated based on the second set of parameters. Data is retrieved from locations within the first memory specified by the sequence of memory addresses and loaded into register files that correspond to respective execution units within a processor.

Efficient data loading in a data-parallel processor

A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.

Method for managing resources in a reconfigurable computer having programmable logic resources where automatically swapping configuration data between a secondary storage device and the programmable logic resources

Housing having shape embedded circuit board

Embedded circuit board

Chip and light emitting diode panel housing

Embedded circuit board housing

Reconfigurable programmable logic device computer system

A method is described herein for designing a circuit using graphic editor software. A graphic design file is generated corresponding to a block diagram created in a graphical user interface associated with the graphic editor software. The block diagram includes a plurality of blocks and a plurality of conduits interconnecting the blocks. A block design file is generated in one of a plurality of formats for each of selected ones of the plurality of blocks in the block diagram. Each of the block design files corresponds to an implementation of its corresponding block. Modifications to any of the graphic design file and the block design files are incorporated into each other under software control.

Graphic editor for block diagram level design of circuits

An apparatus and method for in-system programming of programmable devices includes a device configuration program with adaptive programming source code instructions that characterize device configuration instructions and data. The adaptive source code instructions may include conditional branches, subroutines, variables, configurable arrays, integer operators, and Boolean operators. These features allow for more compact and efficient device configuration instructions and data. An interpreter converts the device configuration program into formatted device configuration instructions and data. The formatted device configuration instructions and data are preferably compatible with IEEE 1149.1 JTAG-BST specifications. The formatted device configuration instructions and data are used to program a programmable device in the manner specified by the adaptive programming source code instructions.

Apparatus and method for in-system programming of integrated circuits containing programmable elements

A method for simulating a portion of a circuit design is described. The circuit design includes a plurality of design files each corresponding to one of a plurality of design entities in the circuit design. A subset of the design entities is selected. The subset of the design entities corresponds to the portion of the circuit design to be simulated. In response to selection of the subset of the design entities, a netlist is generated under software control directly from the design files associated with the subset of the design entities. The portion of the circuit design is then simulated using the netlist.

Methods and apparatus for simulating a portion of a circuit design

A method for upgrading software is described. According to the invention, in response to operation of the software on a first platform, a connection is established between the first platform and a remote platform. Where first version data associated with the software are different from second version data from the remote platform, a portion of the software is overwritten with first updated code from the remote platform.

Method for providing remote software technical support

A method for designing a circuit is described. A block diagram corresponding to the circuit is generated according to an external specification associated with the circuit. Each block in the block diagram has a block specification associated therewith. A design file is generated for each block in the block diagram using the associated block specification and one of a plurality of design file templates. Each block in the block diagram is implemented by editing its corresponding design file. The operation of each block in the block diagram is simulated. A overall design for the circuit is compiled. After the design is compiled, changes are incorporated into the compiled design in response to changes in at least one design file through the use of software links maintained between the compiled design and the design files. A device is then configured according to the compiled design. Generation of the block diagram and the design file for each block, implementation and simulation of each block, compilation of the compiled design, incorporation of changes into the compiled design, and configuration of the device are all done under software control.

Method and apparatus for automated circuit design

Apparatus and method for in-system programming of integrated circuits

A method is described herein for generating a design file corresponding to a design entity in a logic design. An input and an output are specified for the design entity. A design file type is specified. The design file is created and a design file template corresponding to the design file type is copied into the design file. The design file template includes formatting corresponding to the design file type. The input and the output are instantiated in the design file. The designer may then completely specify the design entity in the design file.

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Redwood City, CA, United States of America

Timothy J Southgate