California Institute of Technology

Timothy J Shaw

Bedabrata Pain

Eric R Fossum

Roger Panicacci

Robert H Nixon

Guang Yang

Barmak Mansoorian

Wai-Chi Fang

Chao Sun

Chris Wrigley

Jeffrey W Yu

Brita H Olson

A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.

Single chip camera active pixel sensor

A circuit for reading out a signal from an infrared detector includes a current-mode background-signal subtracting circuit having a current memory which can be enabled to sample and store a dark level signal from the infrared detector during a calibration phase. The signal stored by the current memory is subtracted from a signal received from the infrared detector during an imaging phase. The circuit also includes a buffered direct injection input circuit and a differential voltage readout section. By performing most of the background signal estimation and subtraction in a current mode, a low gain can be provided by the buffered direct injection input circuit to keep the gain of the background signal relatively small, while a higher gain is provided by the differential voltage readout circuit. An array of such readout circuits can be used in an imager having an array of infrared detectors. The readout circuits can provide a high effective handling capacity.

Focal plane infrared readout circuit with automatic background suppression

The array processor includes a grid of individual morphological processing elements formed on a VLSI chip. Each element of the grid includes a photo-detector for directly sensing a pixel of an image projected upon the chip. A signal generated by the photo-detector is sensed by a threshold circuit which outputs a binary value having a value depending upon the intensity of the light detector by the photo-detector. Each element also includes morphological processing circuitry for manipulating the binary value received from the threshold detector in accordance with predetermined morphological processing operations and in accordance with binary values received from adjacent processing elements. After modification of the binary value by application of one or more morphological processing operations, the binary value of each processing element is used to control a respective LCD element for displaying a pixel of a modified image. In this manner, all pixels of a modified image are output in parallel. By implementing the photo-detector, morphological processing circuitry and LCD output all on a VLSI chip, the array processor is capable is achieving real-time processing of two-dimensional images. An embodiment is also described wherein electrical output, rather than an LCD output, is provided.

Array processor for morphological image processing

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Montrose, CA, United States of America

Timothy J Shaw