Microchip Technology Inc.

Timothy J Phoenix

Joseph Alan Thomsen

Igor Wojewoda

Stephen Bowling

Yong Yuenyongsgool

Henry M Pena

Brian E Boles

Manivannan Balu

Steve Bradley

John Bree

Gordon E Luke

Dereck Fernandes

In an embedded device with a plurality of processor cores, each core has a static random access memory (SRAM), a memory built-in self-test (MBIST) controller associated with the SRAM, an MBIST access port coupled with the MBIST controller, an MBIST finite state machine (FSM) coupled with the MBIST access port via a first multiplexer, and a JTAG interface coupled with the MBIST access ports of each processor core via the multiplexer of each processor core.

Multi-processor core device with MBIST

A current compensating bias generator generates a current which follows voltage. The current compensating bias generator has a bias generator circuit for generating a current. A current compensating circuit is coupled to the bias generator circuit for changing a value of the current as a voltage input to the current compensating bias generator is changed. A resistive ladder circuit is coupled to the current compensating circuit for setting a voltage level trip point for the current compensating circuit at which the current compensating circuit is used to change the value of the current.

Current compensating bias generator and method therefor

An improved reprogrammable memory device permits definition of a page within an array of memory cells which is variable in size, erasure of only that data contained within the defined variable page while uneffecting the remaining data in the array of memory cells and reprogramming the defined variable page. The improved reprogrammable memory device with variable page size comprises an array of memory cells where the memory cells are arranged in rows and columns; address decode logic coupled to the array of memory cells for accessing the array of memory cells; amplifier logic coupled to the array of memory cells for amplifying the voltage levels between a plurality of the memory cells and data bus when accessing the array of memory cells; column select logic coupled to the array of memory cells for determining which word from a selected row of the array of the memory cells is accessed and for connecting the plurality of memory cells to the amplifier logic; control signals coupled to the amplifier logic for accessing the array of memory cells; and, block enable signals coupled to the address decode logic for varying page size within the array of memory cells to be erased.

Reprogrammable memory device with variable page size

A full-swing high voltage data latch for operation at relatively high power supply voltages. The full-swing high voltage data latch has a high voltage rail for supplying an upper voltage level and a low voltage rail for supplying a lower voltage level. A latch circuit is coupled to the upper voltage rail and to the lower voltage rail. The latch circuit is used for generating an output signal. The output signal switches with respect to an input signal when the high voltage rail and the low voltage rail operate in a low voltage mode and is latched in a state that the output signal is currently at when the high voltage rail and the low voltage rail changes state from said low voltage mode to a high voltage mode. An input circuit is coupled to the latch circuit for sending an input signal and a complementary input signal to the latch circuit. An output driver circuit is coupled to the latch circuit for receiving the output signal from the latch circuit and for providing a full-swing output data latch signal. The full-swing high voltage data latch ranges from the upper voltage level of the high voltage rail to ground.

Full-swing high voltage data latch

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Gilbert, AZ, United States of America

Timothy J Phoenix