Intel Corporation

Timothy J Jehl

Mark A Schmisseur

Jeff J McCoskey

Hang T Nguyen

Pankaj Kumar

Jay S Heeb

John Alan Miller

Richard Paul Mackey

Mark A Yarch

Delf Atallah

Rahul Shukla

In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.

Mirroring data between redundant storage controllers of a storage system

A system and method of initializing a core processing circuit are disclosed. The core processing circuit is held in a reset state while a reset vector is loaded to one or more registers at a boot address associated with the core processing circuit. The reset vector is loaded from a system memory through a host bridge. The reset vector comprises one or more instructions to initialize the core processing system upon release from a reset state.

System and method of remotely initializing a local processor

Disclosed are a system and method of transmitting data or instructions through a data bus to a memory array associated with a core processing circuit. The memory array may be initially adapted to receive data from the data bus and store the data or instructions received from the data bus. At least a portion of the memory array comprising the stored data or instructions may then be configured as a cache memory of the core processing circuit.

System and method for providing data to multi-function memory

Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and a second portion as a memory accessible by the one or more data transmission devices through a data bus independently of the core processing circuit.

Shared memory array

A method and apparatus for hit-dependent flushing of cacheable memory access operations in a bus controller queue is described. The present invention is implemented in the context of a computer system including a microprocessor coupled to an external memory device through an external bus. The processor includes a processor core for issuing memory access operations, a cache, and a bus controller. The bus controller includes a queue having slots for storing pending memory access operations to be sent out over the external bus. After a first memory access operation is issued, the bus controller stores the first memory access operation in a first queue slot before it is determined whether the first operation hits or misses the cache. The bus controller flushes the first operation from the queue if the first operation hits the cache. In response to the processor core issuing a second memory access operation, the bus controller stores the second memory access operation in the first queue slot if the first operation hits the cache. If, on the other hand, the first operation misses the cache, then the bus controller stores the second memory access operation in a second queue slot. Preferably, the first operation is issued in a first cycle and stored in the first queue slot in a second cycle that immediately follows the first cycle, and the second operation is issued in the second cycle.

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Higley, AZ, United States of America

Timothy J Jehl