International Business Machines Corporation

Texas Memory Systems, Inc.

Other

Timothy J Fisher

Aaron Daniel Fry

Roman Alexander Pletka

Nikolas Ioannou

Sasa Tomic

Charles John Camp

Nikolaos Papandreou

Charalampos Pozidis

Thomas P Parnell

Radu Ioan Stoica

Andrew Dale Walls

Ioannis Koltsidas

Lincoln T Simmons

Kevin E Sallese

Adalberto Guillermo Yanes

Jason Szecheong Ma

Thomas Mittelholzer

Holloway H Frost

James Alexander Fuxa

Lance W Shelton

Van Huynh

Charles A Keller

David A Pierce

Razik S Ahmed

Matthew S Reuter

Cyril Varkey

Matthew R Orr

Ashwitha Krishna Kumar

Robert Edward Galbraith

Gary A Tressler

Cheng-Chung Song

Thomas J Griffin

M Dean Sciacca

Christopher M Dennett

Samuel K Ingram

Bryan Bordeaux Grandy

Jenny L Brown

Austin Eberle

John Carrington Cates

Matt Reuter

Robert W Tillerson

A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller repeatedly dynamically resizes the low-density and the high-density pools based on write utilization of the non-volatile memory.

Storage pool resizing to meet memory endurance targets

A technique for writing data to pages in a QLC block of a QLC NAND flash memory device, where the device comprises a plurality of SLC pages organized in SLC blocks and a plurality of QLC pages organized in QLC blocks. The technique comprises storing received data in SLC pages, dividing equally a QLC block in a predefined number of sub-blocks according to a corresponding QLC page health status of the pages of the QLC block. Upon determining that SLC pages are to be copied from SLC pages to QLC pages, copying device-internal the respective SLC pages to the sub-blocks of the QLC block using device-internal cache registers, where the copying is based on an error-count aware scheme.

Write and retire pages in QLC NAND blocks

A computer-implemented method, according to one embodiment, is for performing garbage collection. The computer-implemented method includes: causing pages in non-volatile memory that are due for garbage collection to be inspected, and causing certain ones of the pages in the non-volatile memory having valid data therein to be identified. Each of the pages of non-volatile memory includes multiple planes, and the valid data is included in one or more of the planes in the respective identified pages. Recirculation requests, that selectively exclude planes in the identified pages that do not include any of the valid data, are further sent to a recirculation pool.

Increased garbage collection granularity for non-volatile memory

A non-volatile memory includes physical blocks each including a respective plurality of cells, where each cell is capable of storing multiple bits of data. A controller maintains dynamically resizable pools of physical blocks, including at least a low-density pool in which cells are configured to store fewer bits and a high-density pool in which cells are configured to store more bits. The controller determines whe ther total utilization of physical blocks is less than a low-density pool utilization threshold above which the high-density pool of physical blocks is utilized for storing host write data and additionally identifies cold in-use logical block address (LBA) regions having low total access frequencies. Based on determining the total utilization of physical blocks is less than the low-density pool utilization threshold, the controller performs data placement of data from the cold in-use LBA regions in blocks of the high-density pool.

Proactive data placement in high density storage by a hybrid non-volatile storage controller

Threshold voltage shift values, or TVS values, are calibrated for a non-volatile memory unit including strings of memory cells organized into memory pages, the memory pages being organized into blocks. The calibration involves a read operation to read a given page of the memory pages, based on given one or more TVS values for the given page. In response to a read failure of the read operation, the calibration determines one or more corrected TVS values based on one or more reference TVS values of one or more reference pages of the memory pages. The calibration subsequently performs a read operation to read the given page based on the one or more corrected TVS values. This calibration exploits TVS values of reference pages to determine corrected TVS values of the failing page, instead of finding appropriate TVS values by repeatedly re-reading the failing page.

Calibration of threshold voltage shift values

Provided are a storage device, system, and method for throttling host writes in a host buffer to a storage device. The storage device is coupled to a host system having a host buffer that includes reads and writes to pages of the storage device. Garbage collection consolidates valid data from pages in the storage device to fewer pages. A determination is made as to whether a processing measurement at the storage device satisfies a threshold. A timer value is set to a positive value in response to determining that the processing measurement satisfies the threshold. The timer is started to run for the timer value. Writes from the host buffer are blocked while the timer is running. Writes remain in the host buffer while the timer is running. A write is accepted from the host buffer to process in response to expiration of the timer.

Throttling host writes in a host buffer to a storage device

A non-volatile memory includes a plurality of cells each individually capable of storing multiple bits of data including bits of multiple physical pages. A controller of the non-volatile memory issues a command to perform a programming pass for a physical page among the multiple physical pages. The controller determines whether or not the programming pass took less than a minimum threshold time and no program fail status indication was received. Based on determining the programming pass took less than a minimum threshold time and no program fail status indication was received, the controller detects an under-programming error and performs mitigation for the detected under-programming error.

Detecting and managing under-program failures in non-volatile memory

Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Generating multi-plane reads to read pages on planes of a storage die for a page to read

A controller of a non-volatile memory detects errors in data read from a particular physical page of the non-volatile memory. Based on detecting the errors, the controller performs a read voltage threshold calibration for a page group including the particular physical page and a multiple other physical pages. Performing the read voltage threshold calibration includes calibrating read voltage thresholds based on only the particular physical page of the page group. After the controller performs the read voltage threshold calibration, the controller optionally validates the calibration. Validating the calibration includes determining whether bit error rates diverge within the page group and, if so, mitigating the divergence. Mitigating the divergence includes relocating data from the page group to another block of the non-volatile memory.

Page group read voltage threshold calibration

A computer-implemented method, according to one embodiment, includes: receiving, in first and second read request buffers corresponding to first and second computer interface links of a data storage system, read requests. Read completion data corresponding to the read requests being performed is also received. The read completion data is allocated between first and second read completion buffers based on which of the read completion buffers has a greater amount of available space therein. Furthermore, the read completion data in the first and second read completion buffers is sent. The first read completion buffer corresponds to the first computer interface link and the second read completion buffer corresponds to the second computer interface link.

Increased read performance for implementations having multiple interface links

A computer-implemented method, according to one embodiment, includes: maintaining a first subset of the plurality of blocks in a first pool, where the blocks maintained in the first pool are configured in SLC mode. A second subset of the plurality of blocks is maintained in a second pool, where the blocks maintained in the second pool are configured in multi-bit-per-cell mode. A current I/O rate for the memory is identified during runtime, and a determination is made as to whether the current I/O rate is outside a first range. In response to determining that the current I/O rate is not outside the first range, the blocks maintained in the first pool are used to satisfy incoming host writes. Moreover, in response to determining that the current I/O rate is outside the first range, the blocks maintained in the second pool are used to satisfy incoming host writes.

Workload based relief valve activation for hybrid controller architectures

A memory controller receives a multi-plane read request and identifies a set of actual read offsets for a set of pages in the multi-plane read request. The memory controller calculates a common read offset using the set of actual read offsets. The memory controller calculates an offset difference for. Each page. Each offset difference reflects the difference between an actual read offset for that page and the common read offset. The memory controller compares a particular page's offset difference to an offset difference threshold. The memory controller categorizes, based on the comparing, a first subset of pages from the set of pages into a single plane group and a second subset of pages from the set of pages into a multi-plane group. The memory controller performs a multi-plane read on the multi-plane group.

Triage of multi-plane read requests

A data storage system provides persistent storage in bulk non-volatile memory. A controller of the data storage system receives a host write command and buffers associated host write data in both a first write cache in non-volatile memory and a mirrored second write cache in volatile memory. The controller destages the host write data to the bulk non-volatile memory from the second write cache but not the first write cache. The controller services relocation write commands requesting data relocation within the bulk non-volatile memory by reference to the second write cache. Servicing the relocation write commands includes buffering relocation write data in the second write cache but not the first write cache and destaging the relocation write data to the bulk non-volatile memory from the second write cache.

Mirroring data in write caches of a controller of a non-volatile memory

A computer-implemented method, according to one approach, includes: determining a current read heat value of each logical page which corresponds to write requests that have accumulated in a destage buffer. Each of the write requests is assigned to a respective write queue based on the current read heat value of each logical page which corresponds to the write requests. Moreover, each of the write queues correspond to a different page stripe which includes physical pages, the physical pages included in each of the respective page stripes being of a same type. Other systems, methods, and computer program products are described in additional approaches.

Data placement in write cache architecture supporting read heat data separation

A RAID controller periodically collects an indication of a current compression ratio achieved by each of a plurality of storage devices within the RAID. The RAID controller determines a placement of data and the parity information within at least one of the plurality of storage devices according to at least one of a plurality of factors associated with the current compression ratio. The RAID controller writes the data and the parity information to the at least one of the plurality of storage devices according to the determined placement.

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Cypress, TX, United States of America

Timothy J Fisher