Motorola Corporation

Freescale Semiconductor,inc.

Timothy J Edwards

David Theodore Blaauw

Abhijit Dharchoudhury

Rajendran Panda

Joseph W Norton

Satyamurthy Pullela

Chanhee Oh

Supamas Sirichotiyakul

Judah L Adelman

David Moshe

A method of improving performance of a dual Vintegrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.

Methods for analyzing integrated circuits and apparatus therefor

A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).

Method for optimizing element sizes in a semiconductor device

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Timothy J Edwards