International Business Machines Corporation

Timothy J Ebbers

Randall L Henderson

Andrew D Bowen

Robert Tamlyn

Nathan R Hiltebeitel

Michael A Aranda

Daniel G Gibbons

Steven William Tomashot

Bob C Liang

David C Tannenbaum

Satish Gupta

Todd Williams

Yoshio Iida

Terence W Lindgren

David W Li

Taggart H Robertson

A random access memory system organized such that multiple pixels may be accessed when one row column address is provided. The random access memory system includes a first group of random access memory devices and a second group of random access memory devices. The first group of devices stores information for pixels on an even horizontal scan line and the second group of devices stores information for pixels on an odd horizontal scan line. An address generator of the random access memory system generates an address to access information from the first group of devices for one pixel and information from the second group of devices for another pixel.

Multi-pixel access memory system

The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for example, a frame buffer A and a frame buffer B. On each serial clock cycle, frame buffer A or frame buffer B for each byte of data may be selected from the register. Each of the selected bytes of data are then passed to a serial output port. In another embodiment, the lower byte of data corresponds to, for example, a frame buffer A and the upper byte corresponds to a frame buffer B. Then either the upper byte or lower byte of data is selected to be output on the serial port. In yet a further embodiment, the serial access memory register is partitioned lengthwise into two sections, each section corresponding to, for example, a frame buffer and the bytes of data correspond to another buffer, then either the lower byte or upper byte is selected to be output on the serial port.

SAM data selection on dual-ported DRAM devices

A graphics display system picking function tracks machine states of pickable primitive operators through the use of a pick stack and machine state memory. The pick stack operates as a stack when accessed by pipeline processors. Pipeline processors can add an element to the stack or remove elements from the stack as structures are processed. Selection or picking of an object causes a graphics control processor to randomly access the pick stack to determine the attributes of a picked primitive. The machine state memory is implemented as a video RAM allowing rapid copying of rows containing machine states for various structure levels in the hierarchy. A first area of the machine state memory stores the states relating to the structures in the hierarchy as they are executed. A second area retains an abbreviated state description for each pickable primitive while a final area contains abbreviated machine state information for picked objects to be echoed by the system. The pick stack and machine state memories operate together to provide rapid pick identification, picked primitive machine state identification, and picked primitive echoing. The use of separate picked primitive echo machine storage allows drawing of the picked primitives without a complete re-traversal of the displayed list. This also results in reduced processing time.

Picking function for a pipeline graphics system using hierarchical

A pick queue and pick detection method that allows non-hierarchical graphic data models and applications to be used with pipelined processing systems. Pretransformed formatting logic is placed prior to pipeline processors to store necessary picking information in a pick queue. A pick tag addressing the pick queue is passed with each graphics order through the pipeline and stored in the pick detect logic. The pick detect logic interrupts the graphics control processor that then accesses the tag register associated with the graphics order and the coordinate counter to address the stored pick information of the order triggering the pick. The graphics processor uses the tag address and coordinate counter to indirectly address the pick queue and retrieve the information that needs to be passed back to the application program. The structure eliminates the requirement to pass all information through the pipeline processors.

Pick data queue for pipelined graphics system

Video random access memory having a random array and serial buffer is employed to speed the replication of structure state information used in the processing of hierarchical graphic data structures. Specialized circuitry in the video RAM and associated VRAM sequencer are used to perform a rapid transfer of structure state information from one row of the VRAM (the parent row) to a second VRAM row (the child row). The VRAM sequencer is modified to perform back to back read data transfer and write data transfer operation in response to a single graphics processor command. The return to previous structure state can be accomplished by readdressing the VRAM row containing the previous structure state.

Memory manager for hierarchical graphic structures

An implementation of a serial access memory register facility which allows the external selection of the portion of the SAM to be scanned out. A control signal is provided which causes the reloading of serial access memory address counter causing the reloading of serial access memory address counter causing the serial scanning to shift from one to another of the serial access memory registers. The result is an ability to select a stopping point when scanning out of the serial access memory. Thus, the present invention implements the ability in a video random access memory to specify both the starting and ending points of the data to be scanned out of the serial access memory. The preferred embodiment replaces the QSF status pin with a control pin to preserve the packaging configuration of standard VRAMs.

Video ram with external select of active serial access register

A system for generating multiple pixels in a single machine cycle employs a plurality of parallel vector generators. Each of the parallel generators is initialized with an error term which is calcualted in accordance with Bresenham's algorithm. The signs of these error terms are then used to determine the region within the first octant of the coordinate system which contains the function for which the pixels are to be generated. The region data, in turn, determine two selectable values for an increment which is to be added to a running error term for each of the parallel generators as multiple pixels are simultaneously generated. The choice of the two possible values to be added to the error term is dependent upon the sign of the error term itself. The sign of the running error term for each vector generator is utilized to form a sequence of binary data which represents the incremental changes in the pixel positions as the pixels are being generated. In a preferred embodiment, the binary data is translated into pixel position data which is then stored in a memory device. Any generated pixel data which cannot be stored in the machine cycle in which it is generated is re-routed for storage in later cycles.

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Shokan, NY, United States of America

Timothy J Ebbers