Hrl Laboratories, LLC

Timothy J Derosier

Jose Cruz-Albrecht

Narayan Srinivasa

Shankar R Rao

Austin F Garrido

A reconfigurable neural circuit includes an array of processing nodes. Each processing node includes a single physical neuron circuit having only one input and an output, a single physical synapse circuit having a presynaptic input, and a single physical output coupled to the input of the neuron circuit, a weight memory for storing N synaptic conductance value or weights having an output coupled to the single physical synapse circuit, a single physical spike timing dependent plasticity (STDP) circuit having an output coupled to the weight memory, a first input coupled to the output of the neuron circuit, and a second input coupled to the presynaptic input, and interconnect circuitry connected to the presynaptic input and connected to the output of the single physical neuron circuit. The synapse circuit and the STDP circuit are each time multiplexed circuits. The interconnect circuitry in each respective processing node is coupled to the interconnect circuitry in each other processing node.

Scalable integrated circuit with synaptic electronics and CMOS integrated memristors

A system for real time bilinear interpolation includes a bilinear interpolation module capable of: generating pixel addresses for original image pixels of an original image needed for performing bilinear interpolation of the original image to form a resized image, wherein the generated pixel addresses assume all the original image pixels of the original image are accessible, and performing bilinear interpolation, and a pixel smart memory module capable: of sequentially receiving original image pixel rows of the original image an original image pixel row a time, predicting which original image pixel rows are needed for performing bilinear interpolation, storing only the needed sequentially received original image pixel rows in a memory, decoding the generated pixel addresses to form decoded addresses to access the needed original image pixel rows stored in the memory, and sending the needed original image pixel rows to the bilinear interpolation module for performing bilinear interpolation.

Efficient hardware design and implementation of image interpolation and resizing for image processing pipeline

A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.

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Colorado, CO, United States of America

Timothy J Derosier