International Business Machines Corporation

Timothy J Charest

Yuen H Chan

Rajiv V Joshi

Antonio R Pelella

John R Rawlins

William Vincent Huott

Mary Prilotski Kusko

Rolf Sautter

Otto M Wagner

Bryan J Robbins

Arthur D Tuminaro

Jatinder K Wadhwa

A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.

SRAM and dual single ended bit sense for an SRAM

A late select circuit topology has pseudo-static circuits that provide fast dynamic circuit operation without the use of dynamic clock timing signals. An output from a selected set is enabled by the conjunction of bit line pulse and set select signal.

Cache late select circuit

A multi-port (e.g., two port) CMOS static random access memory (SRAM) with a local clock driver generating clocks for boundary latches. Local clocks select between address inputs clocked into the boundary latches. A read clock selects and latches a read address in the boundary latches. A second clock latches write addresses and, when appropriate, test data addresses.

Clock driver and boundary latch for a multi-port SRAM

A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Programmable sense amplifier timing generator

A method for preparing a logic structure for random pattern testing is disclosed. In an exemplary embodiment of the invention, the method includes configuring a select mechanism within a data scan chain, the select mechanism configured between a first register in the data scan chain and a second register. A parallel data path is routed within the scan chain, the parallel data path beginning from an input side of the first register, running through the select mechanism, and ending at an input side of the second register. Thus configured, the select mechanism is capable of switching a source path of input data to said second register from a normal data path to the parallel data path. When the parallel data path is selected as the source path of input data to the second register, data loaded into the second register matches data loaded into the first register.

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West Hurley, NY, United States of America

Timothy J Charest