Intel Corporation

Intel Corportion

Timothy J Callahan

Lakshminarayana Pappu

Suketu U Bhatt

Hem Doshi

Hooi Kar Loo

Snigdha Jana

Nandan A Kulkarni

Christopher J Nelson

James Edward Neeb

Tomer Levy

Baruch Schnarch

Stephen Sturges

Bradly L Inman

Sundar V Pathy

Shelby G Rollins

Hiren V Tilala

Matthew Hendricks

Jared Pager

Hat clip flag holder

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Compressed test patterns for a field programmable gate array

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing SoC coverage through virtual devices in PCIe and DMI controllers. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a shuttle transaction and to issue the shuttle transaction onto the device fabric directed toward the serial IO interface; in which the shuttle transaction includes a shuttle header and a shuttle payload having embedded therein one or more passenger transactions for issuance onto the device fabric; in which the virtualized device logic is to receive the shuttle transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to strip the shuttle header from the shuttle transaction to expose the one or more passenger transactions; and in which the virtualized device logic is to issue the one or more passenger transactions onto the device fabric. Other related embodiments are disclosed.

Innovative high speed serial controller testing

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing high speed serial controller testing. For instance, in accordance with one embodiment, there is a functional semiconductor device, comprising: a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; virtualized device logic embedded within the serial IO interface; a transaction originator to originate a transaction and issue the transaction onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transaction at the serial IO interface via the device fabric; in which the virtualized device logic is to modify the transaction received to form a modified transaction; in which the virtualized device logic is to issue the modified transaction onto the device fabric; and in which the modified transaction is returned to the transaction originator. Other related embodiments are disclosed.

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing virtual device observation and debug network for high speed serial IOS. According to one embodiment there is a functional semiconductor device, having therein a serial Input/Output interface (serial IO interface); a device fabric to carry transactions between a plurality of components of the functional semiconductor device; a transaction originator to originate a transactions and issue the transactions onto the device fabric directed toward the serial IO interface; in which the virtualized device logic is to receive the transactions at the serial IO interface via the device fabric and return responsive transactions to the device originator based on the transactions received; signature collection logic to collect signal information based on the transactions carried by the device fabric; and a signal accumulator to generate a test signature based on the signal information collected by the signature collection logic. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing a virtual device observation and debug network for high speed serial IOS

A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.

Low cost inbuilt deterministic tester for SOC testing

A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a unified cache controller, and a control register to selectively mask off access by the unified cache controller to portions of the unified cache. Other embodiments are also described and claimed.

Persistent cacheable high volume manufacturing (HVM) initialization code

Growing community of inventors

Hillsboro, OR, United States of America

Timothy J Callahan