Microsoft Technology Licensing, LLC

Timothy Hume Heil

Chad Balling McBride

Kent D Cedola

Amol Ashok Ambardekar

Larry Marvin Wall

Boris Bobrov

George Petre

Deepak Goel

Xiaoling Xu

Nitin Garegrat

Bogdan Alexandru Burlacu

Derek Edward Davout Gladding

Balamurugan Kulanthivelu Veluchamy

A computing device, including a hardware accelerator configured to receive a first matrix and receive a second matrix. The hardware accelerator may, for a plurality of partial matrix regions, in a first iteration, read a first submatrix of the first matrix and a second submatrix of the second matrix into a front-end processing area. The hardware accelerator may multiply the first submatrix by the second submatrix to compute a first intermediate partial matrix. In each of one or more subsequent iterations, the hardware accelerator may read an additional submatrix into the front end processing area. The hardware accelerator may compute an additional intermediate partial matrix as a product of the additional submatrix and a submatrix reused from an immediately prior iteration. The hardware accelerator may compute each partial matrix as a sum of two or more of the intermediate partial matrices and may output the plurality of partial matrices.

Computing partial matrices at hardware accelerator

Hardware semaphores are utilized to increase the speed with which preconditions are evaluated. On an individual basis, each hardware semaphore can implement a binary semaphore or a counting semaphore. Collections of hardware semaphores can be chained together to implement a chain semaphore that can support multiple conditionals. In addition, hardware semaphores can have the capability, not only of generating an interrupt, but, in addition, being able to generate commands, such as to other semaphores. The implementation of a chain semaphore spanning multiple hardware semaphores can be performed by a compiler at compile time or at run time. An integrated circuit chip can comprise multiple execution units, such as processing cores, and individual ones of the execution units can be associated with multiple hardware semaphores, such as in the form of hardware semaphore arrays. A dedicated network-on-chip enables hardware semaphore communication.

On-chip hardware semaphore array supporting multiple conditionals

An exemplary computing environment having a DNN module can maintain one or more bandwidth throttling mechanisms. Illustratively, a first throttling mechanism can specify the number of cycles to wait between transactions on a cooperating fabric component (e.g., data bus). Illustratively, a second throttling mechanism can be a transaction count limiter that operatively sets a threshold of a number of transactions to be processed during a given transaction sequence and limits the number of transactions such as multiple transactions in flight to not exceed the set threshold. In an illustrative operation, in executing these two exemplary calculated throttling parameters, the average bandwidth usage and the peak bandwidth usage can be limited. Operatively, with this fabric bandwidth control, the processing units of the DNN are optimized to process data across each transaction cycle resulting in enhanced processing and lower power consumption.

Enhancing processing performance of a DNN module by bandwidth control of fabric interface

Techniques are described for encoding symbols using a new algorithm that provides a flexible Huffman tree approximation and that can be used for low latency encoding. For example, the new algorithm can perform encoding using one or more of the following phases: Shannon-based binning, code space optimization, tree completion, and code assignment.

Flexible huffman tree approximation for low latency encoding

Growing community of inventors

Kirkland, WA, United States of America

Timothy Hume Heil