International Business Machines Corporation

Timothy Hume Heil

Giora Biran

Jan Van Lunteren

Christoph Hermann Hagleitner

Jeffrey Powers Bradford

Russell Dean Hoover

Andrew D Hilton

James Allen Rose

Andrew Henry Wottreng

Jason Nathaniel Dale

Robert Allen Shearer

Michael Steven Siegel

Adam James Muff

Ronald P Hall

David James Shippy

Christopher Michael Abernathy

Kimberly Marie Fernsler

Jeffrey Richard Summers

Steven Paul VanderWiel

Eric Oliver Mejdrich

Richard James Eickemeyer

Ganesh Balakrishnan

Ken Van Vu

Charles Luther Johnson

Jon K Kriegel

Anil Krishna

Brian Michael Rogers

Benjamin Herrenschmidt

Chris Abernathy

Timothy John Mullins

Paul Mackerras

Uzi Shvadron

Harold F Kossman

Gordon Bernard Bell

Brian Lee Koehler

Brent Francis Hilgart

Mvv Anil Krishna

Steven P Vanderwiel

Muawya Mohamed Al-Otoom

This disclosure includes a method for performing branch prediction by a processor having an instruction pipeline. The processor speculatively updates a global history register having fetch group history and branch history, fetches a fetch group of instructions, and assigns a global history vector to the instructions. The processor predicts any branches in the fetch group using the global history vector and a predictor, and evaluates whether the fetch group contains a predicted taken branch. If the fetch group contains a predicted taken branch, the processor flushes subsequently fetched instructions in the pipeline following the predicted taken branch, repairs the global history register to the global history vector, and updates the global history register based on branch prediction information. If the fetch group does not contain a predicted taken branch, the processor updates the global history register with a branch history value for each branch in the fetch group.

Global branch prediction using branch and fetch group history

A branch history table cache is a write cache that stores values of branch history counters written to a branch history table. An update to a branch history table counter is reflected in both the branch history table cache and the branch history table. Before a branch history table counter is updated, a check is made to see if the branch history table counter is in the cache. If not, the branch history table counter is updated based on a value of the branch history table counter that was saved during fetch of the branch history table counter. If, however, the branch history table counter value is in the cache, the value in the cache is used to update the branch history table counter. All branches that use the branch history table counter update the correct counter value, improving processor performance by providing more accurate predictions of branches taken.

Branch history cache and method

Load latency speculation in an out-of-order computer processor, including: issuing a load instruction for execution, wherein the load instruction has a predetermined expected execution latency; issuing a dependent instruction wakeup signal on an instruction wakeup bus, wherein the dependent instruction wakeup signal indicates that the load instruction will be completed upon the expiration of the expected execution latency; determining, upon the expiration of the expected execution latency, whether the load instruction has completed; and responsive to determining that the load instruction has not completed upon the expiration of the expected execution latency, issuing a negative dependent instruction wakeup signal on the instruction wakeup bus, wherein the negative dependent instruction wakeup signal indicates that the load instruction has not completed upon the expiration of the expected execution latency.

Load latency speculation in an out-of-order computer processor

A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.

Pattern matching engine for use in a pattern matching accelerator

Software and hardware managed dual rule bank cache for use in a pattern matching accelerator

Methods, apparatus, and product for memory management among levels of cache in a memory hierarchy in a computer with a processor operatively coupled through two or more levels of cache to a main random access memory, caches closer to the processor in the hierarchy characterized as higher in the hierarchy, including: identifying a line in a first cache that is preferably retained in the first cache, the first cache backed up by at least one cache lower in the memory hierarchy, the lower cache implementing an LRU-type cache line replacement policy; and updating LRU information for the lower cache to indicate that the line has been recently accessed.

Memory management among levels of cache in a memory hierarchy

Algorithm engine for use in a pattern matching accelerator

Multiple hash scheme for use in a pattern matching accelerator

Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.

Dynamic adjustment of read/write ratio of a disk cache

Address translation for use in a pattern matching accelerator

Pattern matching accelerator

Local results processor for use in a pattern matching accelerator

A memory hierarchy in a computer includes levels of cache. The computer also includes a processor operatively coupled through two or more levels of cache to a main random access memory. Caches closer to the processor in the hierarchy are characterized as higher in the hierarchy. Memory management among the levels of cache includes identifying a line in a first cache that is preferably retained in the first cache, where the first cache is backed up by at least one cache lower in the memory hierarchy and the lower cache implements an LRU-type cache line replacement policy. Memory management also includes updating LRU information for the lower cache to indicate that the line has been recently accessed.

Growing community of inventors

Rochester, MN, United States of America

Timothy Hume Heil