Western Digital Corporation

Timothy G O'Shaughnessy

Richard William Hull

Kenneth W Ouyang

Victor G Pierotti

David K Chung

Charles Royston Patton, Iii

Michael R Spaur

Mike Spaur

Brian A Wey

Joseph A Souza

A comparator which is used to compare two analog voltages and provide a single ended output comprises three CMOS differential amplifiers. The use of three differential amplifiers provides improved matching of input capacitance, and a reduction in propagation delay over prior art use of a single differential amplifier. The comparator may be adopted for use in certain CMOS processes to extend the maximum operating voltage by limiting the internal node voltages otherwise subject to damage from impact ionization. An alternative embodiment is disclosed for comparing two analog voltages that are outside the power supply voltage range.

Triple comparator circuit

A stability-compensated, integrated-circuit operational amplifier has an open-loop gain versus frequency characteristic which provides stable and accurate closed-loop operation in numerous overall circuits including a CMOS circuit for producing a precision current as a reference to a digital-to-analog converter. The operational amplifier comprises an inverting node and a non-inverting node, and CMOS circuitry defining two differential amplifiers. Each differential amplifier is connected to the inverting node and the non-inverting node. The first differential amplifier has an output node, and produces on the output node an output potential that defines an output signal having a magnitude that is a function of the magnitude of the difference between a first potential at the inverting node and a second potential at the non-inverting node. The second differential amplifier is also connected to the inverting node and the non-inverting node. The second differential amplifier produces a compensation signal. The operational amplifier further includes capacitive circuitry for coupling the compensation signal to the non-inverting node.

Stability-compensated operational amplifier

A DAC embodied in a CMOS integrated circuit converts a multi-bit digital signal to an analog-current signal. A higher-order portion of the digital signal, e.g., the most significant 5 bits of a byte, are decoded separately from the lower-order portion, e.g., the 3 least significant bits. The DAC includes circuitry for producing a first bias voltage, a first set of current sources each biased by the first bias voltage to produce a switchable current having a unit magnitude, and switching circuitry controlled by the decoded lower-order portion to cause a selected number of the unit-magnitude currents to contribute to the analog-current signal. The DAC further includes circuitry for producing a second bias voltage, a second set of current sources each biased by the second bias voltage to produce a switchable current having a multi-unit magnitude, and switching circuitry controlled by the decoded higher-order portion to cause a selected number of the multi-unit-magnitude currents to contribute to the analog-current signal.

Digital-to-analog converter with bit weight segmented arrays

A method for controlling a programmable source of a plurality of string of clock signals, a program is stored with a plurality of different indications of desired frequencies, each indication corresponding to one of the strings of clock signals. The frequency of each of a plurality of oscillator is controlled by the memory content of a separate memory for each oscillator. The content of each memory is adjusted in accordance with the actual frequency of each string, the frequency indicated by the corresponding indication of a desired frequency and a reference.

Programmable multiple oscillator circuit

The transient noise generated at the output drivers of an integrated circuit chip is reduced by maintaining an increasing ramp shaped current through each output driver during the entire transition interval between binary states of a capacitive load. A capacitor fed by a fixed current source is connected across the input of each output driver stage. The fixed current source and capacitor are so selected as to generate across the input of each output driver stage a linear ramp shaped control voltage that regulates the charging/discharging current through the output driver stage and package inductance in the described manner. A specially designed bias circuit reduces the sensitivity of the resulting transient noise to process variations and operating conditions. A feedback connection from the package inductance to the bias control circuit for the fixed current source adjusts the fixed current inversely with the transient noise. A dynamic clamp suppresses voltage spikes extending outside the voltage supply operating range. A bias circuit arrangement compensates for sheet resistivity of the integrated circuit chip. If the resistance value of the sheet drops below a prescribed value, the fixed current is limited so it cannot exceed its designed value.

Method and apparatus for reducing transient noise in integrated circuits

A Schmitt trigger having first and second complementary switches is biased to exhibit hysteresis, switching at a high threshold level when the input signal increases, and switching at a low threshold level when the input decreases. The source driver for the Schmitt trigger is coupled to the input of at least one of the complementary switches by transition circuitry, such that the signal level representing one binary value is shifted closer to the level of the power supply voltage corresponding to such binary value without changing the logical value of the signal from the source driver. In one embodiment, the first inverter is a MOS transistor, the threshold level of which is set by a bias voltage applied to the gate of another MOS transistor. The second inverter is a pair of complementary CMOS transistors. In another embodiment, the first inverter also comprises a pair of complementary CMOS transistors. The threshold level is set by selecting the W/L ratio of the CMOS transistors of the first inverter. In another embodiment the first inverter comprises a differential amplifier.

Schmitt trigger adapted to interface between different transistor

A circuit is provided for realizing multiple precision resistor elements on an integrated circuit by sensing a reference resistor. The circuit contains a first current source which passes a first current through a reference resistor located either on or off of the integrated circuit to generate a reference voltage. The reference voltage is applied to the inverting input of a precision high gain operational amplifier. A second current source is connected to the drain of a first MOS transistor operating in its ohmic region. The second current source is also connected to the non-inverting input of the high gain operational amplifier. The output of the operational amplifier is electrically connected to the gate of the first and second MOS transistors. In operation, a precision resistance is developed across the second MOS transistor which is equal to or some determinable multiple of the resistance of the reference precision resistor located on or off chip. An operational amplifier adaptable to this circuit is also disclosed.

CMOS integrated circuit having precision resistor elements

A Schmitt trigger circuit with independently biased threshold sections includes a drive disabling switch for blocking one of the threshold sections from driving a logic node toward a predetermined logic state. The drive disabling switch is selectively operated so that unidirectional sensitivity to the crossing of a threshold level belonging to its corresponding one threshold section is obtained.

CMOS Schmitt trigger with independently biased high/low threshold

The present invention provides an apparatus and method for allowing an electronic device to drive large values of load capacitance without generating high levels of transient noise. Means are provided for passing a first current through the parasitic inductance of the integrated circuit prior to the activation of the output driver, presoaking the parasitic inductance. Thereafter, when the output driver is activated and the load capacitance discharges through the inductance of the integrated circuit, the first current is removed from as the current from the load capacitor replaces it. Since an initial level of current existed through the inductance, the rate of change of current passing through the inductance during activation of the output driver is maintained approximately constant, thereby reducing the level of transient noise generated by the electronic device.

Method and apparatus for reducing transient noise by premagnetization of

A Schmitt trigger circuit incorporates an MOS transistor connected as an inverter and two switchable currents being provided as the load to the drain of the MOS transistor to determine the switching threshold. For the low-to-high switching threshold, both currents are supplied to the transistor to require a higher gate voltage to cause the transistor to conduct both currents. Once the transistor conducts both currents and the output switches high to low, one of the sources of current is removed to cause the switching threshold to be reduced to a specified low level. The two load currents are provided by two transistors which are connected in a current mirror configuration so that the ratio of the currents provided can be precisely controlled to achieve the desired switching thresholds for the Schmitt trigger circuit.

CMOS Schmitt trigger circuit using ratioed currents to establish

A CMOS Schmitt Trigger circuit includes a differential structure for comparing an input signal with a feedback signal and a feedback circuit for providing the feedback signal with one of two voltage levels. A CMOS switch pair is connected to one or both of the differential structure and feedback circuit to provide power to the circuit only when necessary so as to minimize power consumption.

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Norco, CA, United States of America

Timothy G O'Shaughnessy