Western Digital Technologies, Inc.

Digital Equipment Corporation

Compaq Computer Corporation, Inc.

Eurologic Systems Limited

Sanmina Corporation

Timothy G Lieber

Reuben Michael Martinez

Robert Lester

Austin Striegel

Timothy J Morris

Evan Richardson

Donald Penza

Brian J Purvis

Bernd Lamberts

Remmelt Pit

Jeffrey David Wilke

Zarko Popov

Odie Banks Killen, Jr

Kevin J Lonergan

Paul Orin Amdahl

Eugene McCabe

Michael J Hynes

Jared Tesone

Mike Stolz

Hans O'Sullivan

An approach to identifying poorly performing data storage devices (DSDs) in a data storage system, such as hard disk drives (HDDs) and/or solid-state drives (SSDs), involves retrieving and evaluating a respective set of log pages, such as SCSI Log Sense counters, from each of multiple DSDs. Based on each respective set of log pages, a value for a Quality of Service (QoS) metric is determined for each respective DSD, where each QoS value represents an average percentage of bytes processed without the respective DSD performing an autonomous error correction. In response to a particular DSD reaching a predetermined threshold QoS value, an in-situ repair may be determined for the particular DSD or the particular DSD may be added to a list of candidate DSDs for further examination, which may include an FRPH examination for suitably configured DSDs.

Use of error correction-based metric for identifying poorly performing data storage devices

An approach to identifying problematic data storage devices, such as hard disk drives (HDDs), in a data storage system involves retrieving and evaluating a respective recovery log, such as a media error section of a device status log, from each of multiple HDDs. Based on each recovery log, a value for a Full Recoveries Per Hour (FRPH) metric is determined for each read-write head of each respective HDD. Generally, the FRPH metric characterizes the amount of time a head has spent performing recovery operations. In response to a particular head FRPH reaching a pre-determined threshold value, an in-situ repair can be determined for the HDD in which the head operates. Similarly, in the context of solid-state drives (SSDs), a latency metric is determinable based on time spent waiting on resolving input/output (IO) request collisions, on which an in-situ repair can be based.

Use of recovery behavior for prognosticating and in-situ repair of data storage devices

A dynamic scalable error correction coding (ECC) scheme for a data storage system involves a system controller predicting a type and/or amount of ECC needed to reconstruct data to be stored on a particular data storage device(s) based on operational data integrity information accessed from the array of data storage devices. Thus, redundancy does not need to be allocated unless required. The devices may be logically grouped into subsets according to common characteristics, whereby the prediction made for a device in a subset may be based on the data integrity information from that subset, as well as from other relevant subsets.

System-level error correction coding allocation based on device population data integrity sharing

Non-limiting examples of the present disclosure relate to execution of in-situ manufacturing for a data storage device. In-situ manufacturing is on-location configuration of a data storage device within an operational environment in which a data storage device is being deployed. In-situ manufacturing occurs at any point after a data storage device is shipped from a manufacturing plant or factory. When an operational environment of the data storage device is known, parameters of the data storage device can be configured (or re-configured) on-location within an operational environment to optimize capacity management as well as performance of the data storage device.

Customizing configuration of storage device(s) for operational environment

A chassis input/output (I/O) module adapted for use in a front region of a mass storage chassis assembly is provided. The chassis I/O module in one example includes an I/O module shell, a main I/O connector externally available on the I/O module shell, a plurality of sub-assembly connectors externally available on the I/O module shell, one or more power supply modules, and an interface module electrically coupled to the main I/O connector, the plurality of sub-assembly connectors, and the one or more power supply modules, with the interface module configured to regulate operations of one or more mass storage sub-assemblies installed in the mass storage chassis assembly, regulate provision of electrical power from the one or more power supply modules to the one or more mass storage sub-assemblies, and facilitate exchange of electrical signals between the one or more mass storage sub-assemblies and the main I/O connector.

Chassis input/output (I/O) module for use in front region of mass storage chassis assembly

A side loading enclosure for a rack mount type storage unit is provided. The enclosure provides for easier access to hard disk drives (HDDs) for maintenance and repair as well as the ability to increase the number of HDDs that can be mounted in a single enclosure. The enclosure may include a bottom plate, a pair of side plates, and a pair of end plates. Located within the enclosure are a first row, extending perpendicularly between the pair of end plates, having one or more stacks of HDDs mounted to a first printed circuit board and a second row, extending perpendicularly between the pair of end plates, having one or more stacks of HDDs mounted to a second printed circuit board. The one or more stacks of HDDS in the first row is separate from and located parallel to the one or more stacks of HDDs in the second row.

Side loading enclosure for a rack mount type storage unit

An enclosure services processor card is arranged to selectively split a fiber-channel arbitrated-loop (FC-AL) into two split loops. The card is adapted to plug into a backplane for a rack enclosure and includes a first switch operatively connected to a hub for the FC-AL. The hub comprises a plurality of port bypass circuits, each port bypass circuit being connected to a pair of tracks which in use connect to a respective one of each of the devices comprising the fiber channel arbitrated loop. The hub further comprises a pair of switches operatively controlled by the first switch, the pair of switches being disposed between respective port bypass circuits at which the loop is to be split. In a first state the pair of switches connect the devices in a single loop and in a second state the pair of switches divide the devices into two split loops.

Fiber-channel arbitrated-loop split loop operation

In a high-performance data storage system, an enclosure contains a multiplicity of disk drives, each of which has two high-speed serial data ports. Respective data lines are provided which connect each of the data ports with a respective high-speed data multiplexer. Importantly, each of the multiplexers is also connected with each of two distinct I/O modules. Failure of either I/O module still permits the remaining I/O module to have serial high-speed connectivity with each of the multiplexers, and thus with each of the data ports on each disk drive. Finally, the overall function of the system may be selected as JBOD (Just a Bunch Of Drives), as SAN (Storage Area Network), or NAS (Network Attached Storage), without requiring any mechanical or electronic change other than the I/O modules.

Storage apparatus

A system and method for automatically mapping on a computer display a graphical representation of a physical arrangement of a plurality of computer components in one or more cabinets, each cabinet having one or more shelves for housing the computer components. The status of the components is periodically monitored and the computer display updated accordingly. A graphical user interface is provided for user observation of the physical arrangement and status of computer components in the cabinets, as well as user control of the operational parameters of the components.

Automatic mapping, monitoring, and control of computer room components

A field-reprogammable storage control device has a microcontroller, a write-protected memory which contains a boot code for the storage control device, a rewriteable memory for application code executable by the microcontroller, and a jump function located in both the write-protected memory and the rewriteable memory for movement between the write-protected memory and the rewriteable memory for recover after a processing interruption. The storage control device remains operational using the write-protected memory and the boot code while receiving a new application code from a remote site.

Memory paging scheme for 8051 class microcontrollers

A system and method for determining the physical presence, proper electrical coupling and predetermined identifying characteristics and attributes of various computer system elements and components, including both fixed and removable modules such as field replaceable units ('FRUs'), utilizing a minimum number of signal lines per component. In a preferred embodiment, a voltage divider is established between a first resistance in an environmental monitoring unit ('EMU') and a second resistance in an associated FRU wherein a voltage level taken intermediate the first and second resistances is indicative of a particular FRU attribute.

System and method for determining attributes and coupling

Automatic shelf-to-shelf address assignment is provided for a plurality of disk drive supporting shelves that are removably contained within a multi--shelf cabinet. Error detection apparatus detects failure in the automatic assignment of shelf addresses. An address input of shelf-N receives a shelf addressing voltage from shelf N+1. Shelf-N checks to ensure that the received shelf-N address voltage is within a correct range. Where-N now increases its shelf-N address by one and applies this incremented address to an address input of shelf-N+1. Accuracy of the shelf-N+1 address input is checked, as are the cable/connectors that connect shelf-N to shelf-N+1. ADC and ADC techniques are used, and operation of the automatic address assignment system is timed.

Growing community of inventors

Colorado Springs, CO, United States of America

Timothy G Lieber