Applied Micro Circuits Corporation

Qualcomm Incorporated

Timothy Eric Giorgetta

Alan Michael Sorgi

Daniel M Castagnozzi

Madjid Abdul Hamidi

James Leroy Blair

Simon Sai-Man Pang

A system and method are provided for programming the parallel path width in a serial-to-parallel path transceiver. Initially, the transceiver is programmed to select a link layer (layer 1) protocol, such as Gigabit Ethernet (GBE) or SONET. The method accepts serial digital data in the selected protocol at a serial interface, and differentiates the serial data into units of i bits per unit. Another programmed selection is made between n number of unique data interfaces, where each interface includes a plurality of parallel paths. The serial digital data is assigned to z selected data interfaces and transmitted. In one aspect, the serial data is assigned to m number of parallel path channels, where m is less than, or equal to z, and less than i. In another aspect, the frequency at which each data interface parallel path transmits data is selected.

Serial-to-parallel transceiver with programmable parallel data path width

A system and method are provided for auto-squelching digital communications. The method receives digital information from a source node. If the receive channel is corrupted, an alarm condition is detected that is associated with the received digital information. The method transmits an alarm-condition signal to a destination node, and in response to transmitting the alarm-condition signal, maintains a valid link to the destination node. For example, detecting the alarm condition may include: comparing a frequency associated with the recovered clock signal, with a reference frequency; and, detecting a variance between the recovered clock signal frequency and the reference frequency. Alternately, loss of signal, loss of lock, out of band, and run length alarm conditions may be detected. The alarm-condition signal that is transmitted may be a serial data stream of information such as all '0's data, all '1's data, or alternating &#x201c;0&#x201d;s and &#x201c;1&#x201d;s data for example.

System and method for auto-squelching digital communications

A system and method are provided for selecting loss of signal (LOS) criteria in a serial communications receiver. The method receives a serial stream of digital data and selects LOS criteria. The serial stream of digital data is compared to the selected LOS criteria. In response to the serial stream of digital data failing to meet the selected LOS criteria, a LOS signal is generated. Some examples of the LOS criteria that might be selected include: a 'signal detect' signal received from the source transmitting the serial stream of digital data, a run length test, a signal strength (voltage amplitude) test, harmonic band detection test, and a received data clock test. In one aspect, selecting LOS criteria includes selecting combinations of the above-mentioned LOS criteria, so that the LOS signal is generated in response to failing to meet the combination of selected LOS criteria.

Selectable loss of signal (LOS) criteria

A host device in a data communication system provides a dual-function clock/enable signal at a single output port shared by at least one asynchronous target device and at least one synchronous target device. In the asynchronous operating mode, the host device generates an asynchronous gated-clock signal that facilitates read/write functions of one or more selected asynchronous target devices. In the synchronous operating mode, the host device generates a synchronous clock-gate signal that facilitates read/write functions of one or more selected synchronous target devices. The target devices and the host device share both a common data bus and a common clock bus. The host device supplies the dual-function clock/enable signal on the common clock bus.

Dual function clock signal suitable for host control of synchronous and asynchronous target devices

A method is provided for organizing a communications frame structure with selectable synchronization words. The frame structure includes a header section for overhead bits. The number of bits, position of those bits, and the content of the bits used for synchronization of the frame structure are selected from the header section for use in transmitting information. On the receiving end of the transmission, the same number, position, and content of bits are selected to synchronize the received information stream. A communications repeater and system using the above-described selectable frame synchronization structure method is also provided.

Transposable frame synchronization structure

A method for analyzing Gigabit Ethernet (GBE) and fiber channel protocol communications is provided which provides a more detailed understanding of the errors, than that provided under the IEEE 802.3z standard. The method creates an additional parity error signal which is not specified under the IEEE 802.3z standard. The parity error signals and IEEE 802.3z invalid code word signals are used to provide an analysis of whether the underlying communication errors are a result of 8B/10B coding word errors or running disparity errors. A system and apparatus to monitor performance in accordance with the above-mentioned method is also provided.

Gigabit ethernet performance monitoring

A computer-implemented method of quickly determining whether two or more electronic devices are communicatively compatible is described. The method includes reading a plurality of input parameter data associated with a first electronic device and a plurality of output parameter data associated with a second electronic device; analyzing the pluralities of input and output parameter data by determining whether they comply with a plurality of communication compatibility rules; generating results from the analysis; and providing a visual display of the results. The results identify which input and output parameter data do and do not comply with these rules, and thus whether and to what extent the devices are communicatively compatible. As one example, the input parameter data of the first electronic device may include a maximum high input voltage V, a minimum high input voltage V, a maximum low input voltage V, and a minimum low input voltage V; and the output parameter data of the second electronic device may include a maximum high output voltage V, a minimum high output voltage V, a maximum low output voltage V, and a minimum low output voltage V. In this case the communication compatibility rules specify that V&#x2266;V, V&#x2267;V, V&#x2266;V, and V&#x2267;Vfor device compatibility.

Methods and apparatus for determining whether electronic devices are communicatively compatible

A method is provided for creating an auxiliary link embedded in the overhead structure of a primary data link. The primary data link is organized in a frame structure which includes data sections and header sections. Information in the header sections is used to synchronize and capture transmitted messages. However, not all the overhead bits need be used for synchronization. Bits may be selectively &ldquo;robbed&rdquo; from the header section and used to transfer information in an auxiliary data link. The number of bits that are used to support the auxiliary data link, as well as the placement of these bits in the header section are both selectable. An apparatus, specifically the AMCC Performance Monitor IC, has also been described which supports the establishment of an auxiliary data link in accordance with the above-mentioned method.

Programmable synchronization structure with auxiliary data link

A method is provided for selectively inserting data, from a plurality of data sources, into a transmitted stream of information. The method makes a first selection to store data from at least a first and second source in a TX_OH memory. Then, the method makes a second selection, inserting the data stored in the TX_OH memory, into a transmitted stream of information. Typically, the information stream is a SONET/SDH protocol communication in a frame structure which includes overhead bytes. The provided method permits the overhead bytes of a received SONET/SDH communication to be selectively replaced with overhead bytes from either an FPGA or microprocessor source. An apparatus and system for arbitrating between multiple data sources in a communication transmission is also provided.

Multi-port data arbitration control

A method for monitoring the performance of digital communications has been provided which selectively performs Forward Error Corrections (FEC)s on the monitored data. In addition to selectively performing FEC, the process selectively decodes input data, and selectively encodes data for transmission. The decoding, FEC, and encoding operations can also be combined. Further, the process selectively performs evaluations of SONET/SDH protocol communications, Gigabit Ethernet (GBE), and other fiber channel communications, in addition to the selective decode/FEC/encode processes. An apparatus and system to enable the above-mentioned selective monitoring process has also been provided.

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San Diego, CA, United States of America

Timothy Eric Giorgetta