Emc Corporation

Timothy Dorr

Stephen Edward Strickland

John Victor Burroughs

Michael Robillard

Steven D Sardella

Paul H Maier, Jr

Michael A Faulkner

Sharon Smith

Robert L Halliday

Louise Schwabe

A speed control system is provided for controlling temperature within a chassis. The chassis includes therein a temperature sensing device for producing a temperature signal representative of temperature within the chassis, a fan, and a fan speed controller. The fan speed controller produces a nominal fan speed control signal comprising a train of pulses, successive pulses having a duty cycle related to the temperature signal produced by the temperature sensing device, such time durations decreasing with increasing temperature. The speed control system includes a decoupling circuit responsive to the nominal fan speed control signal for, in response to relatively a low duty cycle, coupling the nominal fan control signal to an output of the decoupling circuit, and, in response a relatively high duty cycle, producing a preset fan speed signal at the output of the decoupling circuit. The fan has a speed in accordance with the signal at the output of the decoupling circuit.

Data storage system having cooling fan speed protection

An interface for coupling data between a host computer/server and a bank of disk drives. The interface includes a chassis having disposed therein: a pair of storage processors adapted for coupling to the host computer/server; and, a pair of management controllers in communication one with the other through a communication link. The management controllers monitor elements of the interface including fans and power supplies and control such elements in response to massages passing between the management controllers.

Data storage system having plural storage processors in a single chassis

A data storage system includes a disk drive array including a plurality of disk drives; a first storage processor for controlling the operation of the data storage system; a second storage processor for controlling the operation of the data storage system; a first arbiter for controlling communication of data from the first storage processor and the second storage processor to a first group of disk drives of the disk drive array; and a second arbiter for controlling communication of data from the first storage processor and the second storage processor to a second group of disk drives of the disk drive array. Selected data is redundantly stored on disk drives in the first group of disk drives and the second group of disk drives, such that, upon failure of the first arbiter, the selected data is available to the first storage processor and the second storage processor through the second arbiter.

High availability data storage system

Disk drive spin-up is staggered to reduce peak power requirements. Spin-up of the drives is controlled by selectively delaying voltage inputs to the disk drives. Alternately, spin-up of the drives is controlled by staggering the timing of communications to the disk drives.

Disk drive input sequencing for staggered drive spin-up

A system for detecting a fault in a power supply having at least one power supply unit and a redundant power supply unit. The system includes a printed circuit board and a common voltage bus disposed on the printed circuit board. A plurality of diodes is disposed on the printed circuit board having first electrodes connected to the common voltage supply bus. The diodes have second electrodes connected to a corresponding one of the at least one power supply unit and the redundant power supply unit. The diodes are connected to the common bus in a logic OR configuration. A controller, disposed on the printed circuit board, is fed by a voltage at the second electrode of a corresponding one of the diodes and a reference voltage for determining whether the voltage at the second electrode of the corresponding one of the diodes is producing a predetermined voltage relative to the reference voltage.

Power supply system

A data storage system has a first storage processor, a second storage processor, and a communications subsystem. The communications subsystem has (i) an interfacing portion interconnected between the first storage processor and the second storage processor, (ii) a clock circuit coupled to the interfacing portion, and (iii) a controller coupled to the interfacing portion and the clock circuit. The controller is configured to enable operation of the interfacing portion to provide communications between the first and second storage processors, sense a failure within the clock circuit, and reset the interfacing portion in response to the sensed failure to enable one of the first and second storage processors to continue operation. Such resetting of the interfacing portion prevents the remaining storage processor from locking up, thus freeing that storage processor so that it is capable of continuing to operate even after the failure.

Techniques for maintaining operation of data storage system during a failure

In a highly available environmental monitoring system, several slave devices are associated with either a fast polling list or a slow polling list. The fast polling list is polled by a master device more frequently than the slow polling list. A slave device is associated with the fast polling list if the slave device responds to a poll from the master device within a time period, and is associated with the slow polling list if the slave device does not respond to the poll from the master device within the time period. Furthermore, several control devices arbitrate to determine which shall be the master device for controlling several serial buses. The master device periodically switches between the plurality of serial buses to communicate with slave devices.

Techniques for accessing devices through a set of serial buses

A method and apparatus is described for controlling accesses to a shared resource. An arbitration mechanism uses a register, accessible by each device sharing the resource. The register may be written by the device to request access to the resource, and read by the device to determine whether access to the resource has been granted. Advantageously, the register includes an override bit, which may be used by either device to override the peer device's request for the shared resource. In addition, the register includes a reset bit that may be used to reset arbitration logic controlling the access to the shared logic. The register is used by a straightforward arbitration mechanism that includes only IDLE and GRANT states for each device coupled to the shared resource. Such an arrangement provides a low cost method of controlling accesses to a shared resource.

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Lancaster, MA, United States of America

Timothy Dorr