International Business Machines Corporation

Globalfoundries Inc.

Ultratech, Inc.

Other

Advanced Micro Devices Corporation

Globalfoundries U.S. 2 LLC

Timothy Dooling Sullivan

Jeffrey P Gambino

Timothy Harrison Daubenspeck

Wolfgang Sauter

Christopher David Muzzy

Fen Chen

Ping-Chuan Wang

Baozhen Li

Tom C Lee

Mukta G Farooq

Max Gerald Levy

Stephen Peter Ayotte

Matthew D Moon

Zhong-Xiang He

Charles Leon Arvin

Raschid Jose Bezama

David L Questad

Paul Stephen McLaughlin

Lijuan Zhang

David C Thomas

Joseph M Lukaitis

Anthony K Stamper

Ronald G Filippi

Steven Lorenz Wright

Thomas Anthony Wassick

Krystyna Waleria Semkow

Ethan Harrison Cannon

Alvin Wayne Strong

Hazara Singh Rathore

Jonathan Daniel Chapple-Sokol

Timothy M Sullivan

Kimball M Watson

Birendra N Agarwala

Claude Louis Bertin

John Edward Cronin

William R Tonti

Jed Hickory Rankin

Robert Russell Robison

Erik L Hedberg

James Gardner Ryan

John Matthew Safran

David L Harmon

Chih-Chao Yang

Lawrence Alfred Clevenger

Terence B Hook

Edmund Juris Sprogis

William Thomas Motsiff

Thomas L McDevitt

William Joseph Murphy

Kaushik Chanda

Du Binh Nguyen

Ekta Misra

Cathryn Jeanne Christiansen

Richard Andre Wachnik

Steven H Voldman

John J Ellis-Monaghan

John Atkinson Fifield

Hariklia Deligianni

Christopher Vincent Jahnes

David Louis Harame

Minhua Lu

Anthony Correale, Jr

William F Clark, Jr

Michael D Potter

Russell J Houghton

Robert Allen Groves

Panayotis Constantinou Andricacos

David Lewis Gardell

Brian Richard Sundlof

Rosemary A Previti-Kelly

Ian D Melville

David Michael Audette

William Francis Landers

Xiaojin Wei

Harry David Cox

David Earle Seeger

William A Klaasen

Daniel Scott Vanslette

John M Aitken

Robin A Susko

Jennifer L Lund

Ronald Jay Bolam

Daniel C Edelstein

Dureseti Chidambarrao

Alvin Jose Joseph

Kenneth Parker Rodbell

Paul Stephen Andry

Chandrasekharan Kothandaraman

Bucknell Chapman Webb

Hanyi Ding

Thomas M Shaw

Eric Jeffrey White

Paul Francis Fortier

Kenneth Jay Stein

Yanfeng Wang

Robert Rosenberg

Bruce Walter Porth

Andrew Tae Kim

Cornelia Kang-I Tsang

Thomas Benjamin Faure

An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Electromigration monitor

A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.

A probe tip structure that decreases the accumulation rate of Sn particles to the probe tip and enables considerably more efficient and complete laser cleaning is disclosed. In an embodiment, the probe structure includes an array of probe tips, each probe tip having an inner core; an interfacial layer bonded to the inner core; and an outer layer bonded to the interfacial layer, wherein the outer layer is resistant to adherence of the solder of the ball grid array package.

Solder bump array probe tip structure for laser cleaning

Methods and apparatus for joining a chip with a substrate. The chip is moved by with a pick-and-place machine from a first location to a second location proximate to the substrate over a first time. In response to moving the chip in a motion path from the first location to the second location, a plurality of solder bumps carried on the chip are liquefied over a second time that is less than the first time. While the solder bumps are liquefied, the chip is placed by the pick-and-place machine onto the substrate.

Chip joining by induction heating

An apparatus and an associated method. The apparatus includes a chuck, an array of three or more ultrasonic sensors, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

Centering substrates on a chuck

Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure can include: a photosensitive polyimide (PSPI) layer including a pedestal portion; a controlled collapse chip connection (C4) bump overlying the pedestal portion of the PSPI layer; a solder overlying the C4 bump and contacting a side of the C4 bump; and an underfill layer abutting the pedestal portion of the PSPI and the C4 bump, wherein the underfill layer and the solder form a first interface separated from the PSPI pedestal.

Extrusion-resistant solder interconnect structures and methods of forming

An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chamber, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.

A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.

Wiring structures, methods for providing a wiring structure, and methods for distributing currents with a wiring structure from one or more through-substrate vias to multiple bumps. A first current is directed from a first through-substrate via of a first electrical resistance through a first connection line to a first bump and directing a second current from the first through-substrate via through a second connection line of a second electrical resistance to a second bump. The first connection line has a first length relative to a first position of the first bump and a first cross-sectional area, the second connection line has a second length relative to a first position of the second bump and a second cross-sectional area, the second length is different from the first length, and the second cross-sectional area is different from the first cross-sectional area.

Three-dimensional integrated circuit integration

A handle wafer which prevents edge cracking during a thinning process and method of using the handle wafer for grinding processes are disclosed. The handle wafer includes a body portion with a bottom surface. A square edge portion is provided about a circumference of the bottom surface.

Handle wafer

An apparatus and method for centering substrates determining on a chuck. The apparatus includes a chuck in a process chamber, the chuck configured to removeably hold a substrate for processing; an array of two or more ultrasonic sensors arranged in the process chamber, each ultrasonic sensor arranged relative to the chuck so as to send a respective ultrasonic sound wave to a respective preselected region of the substrate and receive a respective return ultrasonic sound wave from the preselected region of the substrate; and a controller connected to each ultrasonic sensor and configured to compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave from each ultrasonic sensor.

Apparatus and method for centering substrates on a chuck

A spacer structure formed adjacent a solder connection which prevents solder extrusion and methods of manufacture are disclosed. The method includes forming a solder preform connection on a bond pad of a chip. The method further includes forming a spacer structure on sidewalls of the solder preform connection. The method further includes subjecting the solder preform connection to a predetermined temperature to form a solder connection with the spacer structure remaining thereabout.

Structure to prevent solder extrusion

Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, a method can include: providing a precursor interconnect structure having: a photosensitive polyimide (PSPI) layer; a controlled collapse chip connection (C4) bump overlying the PSPI layer; and a solder overlying the C4 bump and contacting a side of the C4 bump. The method can further include recessing a portion of the PSPI layer adjacent to the C4 bump to form a PSPI pedestal under the C4 bump. The method can additionally include forming an underfill abutting the PSPI pedestal and the C4 bump, wherein the underfill and the solder form an interface separated from the PSPI pedestal.

Growing community of inventors

Underhill, VT, United States of America

Timothy Dooling Sullivan