National Semiconductor Corporation

Via Technologies, Inc.

Texas Instruments Corporation

Via-cyrix, Inc.

Timothy Don Davis

Joseph Douglas Wert

Michael John Shay

Richard L Duncan

Martin S Michael

Kent Bruce Waterson

Gordon Force

Thomas M Norcross

Timothy A Short

Mark Douglas Koether

Ponnarith Pok

Dan E Daugherty

Hon C Fung

Roman Baker

J Scott Johnson

Ahmed Masood

An example apparatus includes: a signal terminal for inputting a signal or for outputting a signal; functional circuitry coupled to the signal terminal; a positive supply rail for supplying a positive voltage; a ground supply rail for supplying a ground voltage; a first electrostatic discharge protection circuit coupled between the positive supply rail and the ground supply rail; a second electrostatic discharge protection circuit coupled between the signal terminal and the ground supply rail; an enable circuit coupled to the signal terminal and to the positive supply rail; and a common trigger circuit having a trigger output signal coupled to the first electrostatic discharge protection circuit and to the second electrostatic discharge protection circuit. Additional apparatus and methods are disclosed.

Method and apparatus for low clamping voltage ESD solution for transient sensitive applications

Circuits and methods for protecting a circuit from an electrostatic discharge (ESD) event are disclosed herein. One such method includes detecting when a circuit to be protected is powering up and disabling an output driver of the circuit to be protected when the circuit is powering up. The power up sequence, for example, may be the result of a sensed ESD event. In addition, the present disclosure includes a circuit that comprises an ESD sensing circuit and a disable circuit. The ESD sensing circuit includes an RC circuit connected between VDD and VSS and a first inverter connected between a second inverter and a node that connects a resistor with a capacitor of the RC circuit. The disable circuit includes a first PMOS transistor and a first NMOS transistor, the first PMOS transistor configured to receive an EN signal from the second inverter, and the first NMOS transistor configured to receive ansignal from the first inverter. The first PMOS transistor is further configured to connect a second PMOS transistor to VDD when EN is low, and the first NMOS transistor is further configured to connect a second NMOS transistor to VSS whenis high.

Protecting circuits from electrostatic discharge

A circuit for voltage level translation with zero static current is disclosed for interfacing devices at one supply voltage with devices at another supply voltage. The translation is achieved by using a modified current mirror circuit such that the current mirror is effectively turned off when the output reaches a steady state condition.

Zero-bias-power level shifting

A method and system is disclosed for minimizing data array accesses during a read operation in a cache memory. The cache memory has one or more tag arrays and one or more data arrays. After accessing each tag array, a selected data array is identified, and subsequently activated. At least one predetermined data entry from the activated data array is accessed, wherein all other data arrays are deactivated during the read operation. In another example, the cache memory is divided into multiple sub-groups so that only a particular sub-group is involved in a memory read operation. By deactivating any many circuits as possible throughout the read operation, the power consumption of the cache memory is greatly reduced.

Method and system for cache power reduction

A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The recoded portions of the second operand are used to select what factor of the first operand to use in forming the partial product terms. The partial product terms are added using carry save addition, with the least significant bits being used to form the least significant bits of the final product. The most significant bits of the final product are then formed by adding the carry save data from the partial product summations. The present invention performs squaring operations used in exponentiation functions by shifting the first operand value (A) by one bit to form twice that value (2*A) prior to multiplying by the second operand (B) to form the 2*(A*B) term needed in such calculations. This shifting is performed in the multiplexer used to select the appropriate factor of the first operand for each partial product term, rather than after the accumulation of the final product term.

Booth multiplier with squaring operation accelerator

A circuit for power arbitration, low battery voltage detection, and the operation of battery backed circuitry for systems in which the system power supply voltage range overlaps that of a battery source. A voltage regulator is used to regulate the battery voltage so that the voltage range of the battery source is below the voltage range of the system supply. The regulator is based on a silicon-bandgap referenced methodology and consumes an insignificant amount of current so that the battery life is not appreciably affected. The regulator also has a smaller variation in its output voltage than the battery. A temperature and supply voltage compensated voltage is produced by the combination of a subthreshold current source, parasitic bipolar devices, and voltage buffering, and used to provide a voltage source for the battery backed circuitry of the system. The regulated voltage is set to a value lower than the system supply and serves as the battery supply input for the power arbitration circuitry. The regulated voltage permits the internal power arbitration scheme of the present invention to be equivalent to existing arbitration circuits even though the battery and system supply voltage ranges overlap.

Low power real-time clock circuit having system and battery power

Input/output and local area network functions are combined into a single integrated circuit on a single semiconductor (e.g., a single piece of silicon). Preferred system embodiments on a single integrated circuit are typically placed inside a host system (e.g., a personal computer based on Intel.RTM.'s 286, 386, 486, and Pentium microprocessors) and interrelate with standard operating systems (e.g., Microsoft.RTM.'s DOS, IBM.RTM.'s OS/2) on traditional, commonly used bus architectures (e.g., Industry Standard Architecture and Enhanced Industry Standard). Local area network circuitry and input and output circuitry are both coupled to at least one host system (and indirectly to potentially any number of host systems tied together via the local area network system) via a common data bus. The input and output circuitry couples the host system to at least one input/output channels. Examples of the types of input/output channels are a first serial interface, a second serial interface, a parallel port, a hard drive, a floppy drive, and/or any combination thereof.

Combination of input output circuitry and local area network systems

A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The loading of the second operand continues while the previously loaded portions of the operand are recoded and the partial products based on those recoded portions are generated and accumulated.

Accelerated booth multiplier using interleaved operand loading

A multiplier which uses Booth recoding to multiply large word length operands. A first operand is fully loaded into a shift register. The loading of the second operand is then begun, with the recoding operation beginning after the loading of the minimum number of bits of the second operand required for the first stage of the recoding. The recoded portions of the second operand are used to select what factor of the first operand to use in forming the partial product terms. The partial product terms are added using carry save addition, with the least significant bits being used to form the least significant bits of the final product. The most significant bits of the final product are then formed by adding the partial sum and carry save data from the partial product summations. This summing of the partial sum and carry save data is performed using a data bus width carry look ahead adder instead of the adders used for the partial product accumulation, as is done in typical Booth recoding multipliers.

Booth multiplier using data path width adder for efficient carry save

A multiplier which uses Booth recoding to multiply large word length operands. The multiplier can be divided into three functional modules: 1) operand loading module, 2) Booth partial product calculation and accumulation module, and 3) accumulator shift function module which builds the final 512 bit product. Each of the three stages is clocked independently of the others. The clock signals used to control the data processing operations and flow of data through the registers and adders are gated so that those registers which are needed for the stage of the multiplication operation being executed are clocked, while the other registers are not enabled.

Power efficient booth multiplier using clock gating

A secure time keeping peripheral device is for synchronizing a time reference clock signal to a system clock signal and is especially suited for use in low-power processor applications. Time reference circuitry adjusts a time reference counter held therein responsive to transitions of the time reference clock signal. At least one system time register is connected to the time reference circuitry to receive the time reference counter responsive to transitions of a synchronizing signal. Synchronizing signal generating circuitry is connected to receive the system clock signal and to provide the synchronizing signal, synchronous to the system clock signal, when an externally provided enable signal is asserted to the synchronizing signal generating circuitry. Since the system time register circuitry is only sampled when the externally provided enable signal is asserted (e.g., when the processor needs to determine the value of the 'real time clock'), power consumption by the secure time keeping device is greatly reduced relative to power consumption of conventional secure time keeping devices.

Secure time keeping peripheral device for use in low-power applications

The present invention is embodied in a Secured Processing Unit (SPU) chip, a microprocessor designed especially for secure data processing. By integrating keys, encryption/decryption engines and algorithms in the SPU, the entire security process is rendered portable and easily distributed across physical boundaries. The invention is based on the orchestration of three interrelated systems: (i) detectors, which alert the SPU to the existence, and help characterize the nature, of a security attack; (ii) filters, which correlate the data from the various detectors, weighing the severity of the attack against the risk to the SPU's integrity, both to its secret data and to the design itself; and (iii) responses, which are countermeasures, calculated by the filters to be most appropriate under the circumstances, to deal with the attack or attacks present. The present invention, with wide capability in all three of the detectors, filters and responses, allows a great degree of flexibility for programming an appropriate level of security/policy into an SPU-based application.

Programmable distributed personal security

A Pierce crystal oscillator circuit for a digital integrated circuit has a capacitance element (such as a field effect capacitor) of an appropriate capacitance value disposed on-board the integrated circuit. One lead of the capacitance element is coupled to the input lead of the gain stage of the Pierce oscillator circuit whereas a second lead of the capacitance element is coupled to the output lead of the gain stage. Providing the capacitance element facilitates oscillator startup and reliability by effectively eliminating the upper gain limit for oscillation. Specific circuit embodiments are also disclosed.

Pierce crystal oscillator having reliable startup for integrated circuits

A low-power crystal oscillator circuit is disclosed that includes an amplifier section having a switchable compensation network. In one embodiment, the oscillator circuit incorporates inverter amplifiers to generate a square-wave output signal that can be used, for example, as a clock signal to drive microprocessors and other digital circuitry. The invention takes advantage of the observation that, if the uncompensated bandwidth is not too excessive, compensation is only needed at start-up to ensure oscillation at the desired crystal frequency. Once the desired oscillation is attained, most of the oscillation cycle occurs during the non-linear regions of the amplifier. These non-linear regions are characterized by low gain, thus suppressing any spurious oscillation. The compensation network is removed after start-up to reduce power consumption.

Oscillator having controllable frequency compensation for suppressing

A signal line driver circuit having an input signal buffer and an open collector output circuit configuration and a method are provided for receiving an input signal and causing the output to pull down the voltage potential of a signal bus line while sinking an output current therefrom at a substantially constant output voltage with a substantially constant input-to-output signal propagation delay variation over variations in operating temperatures. A portion of the output current which is to be sunk from the signal bus line is advantageously used as the current supply for the input signal buffer circuitry. The input signal buffer circuitry uses metal oxide semiconductor field effect transistors in parallel with a bipolar junction transistor to take advantage of their mutually inverse conductivity vs. temperature characteristics, thereby ensuring that the output current sinking capability, output voltage range and input-to-output signal propagation delay variation remain substantially constant over a wide operating temperature range.

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Arlington, TX, United States of America

Timothy Don Davis