Adtran Gmbh

Timothy David Rochell

Dennis B McMahan

Richard A Burch

Neil M Jensen

Robert James Toth

Kevin W Schneider

Michael D Turner

Jason N Morgan

Michael Scott Sansom

A data transmission scheduler subsystem for a multi-channel bank communication system architecture contains a plurality of 'per port' schedulers. Each per port scheduler is resident in the system's primary channel bank, and is operative to controllably cause customer-destined data, that has been buffered from a communication network into switch fabric storage circuitry of the primary channel bank, to be controllably read out for downlink transmission to associated destination data ports of the channel banks at the destination data ports' data rates.

Primary channel bank-resident mechanism for scheduling downstream data transmissions to ports of multiple channel banks

A policing engine for use in a telecommunication equipment shelf is operative to control the rate at which customer-sourced ATM packets are passed to buffers associated with different classes of service to which customers may subscribe. The policing engine examines the rate at which ATM cells are supplied to it from the line card ports, whether the cells are AAL5 cells, and how full are the buffers into which the cells are to be written. If cells are supplied to the policing engine at a rate faster than prescribed peak or sustained cell rates, or if the cell buffer begins to fill up, the policing engine controllably discards incoming cells, thereby effectively 'throttling' the cell flow rate through it.

Policing engine providing dynamic adjustment of peak and sustained data cell rates and efficient transfer of AAL5 cells

A single switch fabric-based, multi-channel bank digital subscriber line access multiplexer includes a master channel bank containing a master switch module in which the switch fabric and a downstream-directed traffic scheduler reside, and one or more expansion channel banks that are linked with the master channel bank by way of upstream and downstream communication links. Distributed among the channel banks are respective policing mechanisms and cell rate control mechanisms that control upstream-directed communications from line card ports of each expansion channel bank to the switch fabric. Downstream data transmissions are locked to network timing, and are scheduled by a centralized scheduling mechanism resident in the master channel bank.

System architecture for linking channel banks of a data communication system

An inter-channel bank addressing and identification protocol, for use with a multi channel bank, digital subscriber line access multiplexer (DSLAM), enables the control processor of a master channel bank to selectively communicate with control processors of subtended slave channel banks, and allows a subtended slave shelf to retain provisioning information, irrespective of a change in shelf location or removal of a subtended slave shelf between the master shelf and another subtended slave shelf. The inter-channel bank addressing and identification protocol uses a shelf address code that is controllably incremented or decremented during the transport of a packet between the master and a slave shelf. In addition, a shelf address code is assigned each slave shelf during initialization. These two codes enable the master to track which channel bank is in which shelf bay.

Method and system for preserving channel bank provisioning information when unit location changes within multi-shelf equipment rack

A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.

Method and apparatus for removing digital glitches

The currently defined industry standard framing structure for 2B1Q ISDN signaling, at 160 kilobaud, provides 128 kbps for a customer (B B ) data channel, and 16 kbps for a data (D) channel. Of the remaining 16 kbps non payload bandwidth, 4 kbps are used for overhead maintenance data. Eight kbps of the remaining 12 kbps of non payload bandwidth, that customarily transport a repeated framing pattern, are usurped for the transport of an auxiliary compressed (from 64 KHz to 8 KHz) digitized voice POTS channel, that is sufficient to transport toll quality voice. The remaining framing pattern bandwidth is adequate prevent an unacceptable reduction in bit error rate.

Use of robbed framing bits to provide secondary pots channel over extended range ISDN communications network

A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.

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Elkmont, AL, United States of America

Timothy David Rochell