Texas Instruments Corporation

Timothy David Anderson

Kai Chirca

Joseph R Zbiciak

Duc Quang Bui

Naveen Bhoria

Pete Michael Hippleheuser

Mujibur Rahman

Abhijeet Ashok Chachad

Matthew D Pierson

David Matthew Thompson

Daniel Brad Wu

Joseph Raymond Michael Zbiciak

Peter Richard Dent

Soujanya Narnur

Todd T Hahn

Alan Davis

Son Hung Tran

Sanjive Agarwala

Jonathan (Son) Hung Tran

Asheesh Bhardwaj

Charles Lance Fuoco

David E Smith

Shriram D Moharil

Raguram Damodaran

Ramakrishnan Venkatasubramanian

David A Comisky

Mel Alan Phipps

Arthur John Redfern

Lewis Nardini

Dheera Balasubramanian Samudrala

Dheera Balasubramanian

Ashish Rai Shrivastava

Amitabh Menon

Eric Biscondi

Paul Daniel Gauvreau

Sahithi Krishna

Gary L Swoboda

Donald Edward Steiss

Chenchi Luo

Reid E Tatge

Jelena Milanovic

Christopher L Mobley

William Franklin Leven

Zhenhua Yu

Pramod Kumar Swami

Jonathan H Shiell

David J Hoyle

Jose Luis Flores

Amritpal Singh Mundra

Alan David Hales

Shyam Jagannathan

Brian Jason Karguth

Neelima Muralidharan

Djordje Senicic

Due Quang Bui

Manisha Agarwala

Steven D Krueger

Joel J Graber

David Quintin Bell

David Edward Smith, Jr

Simonjit Dutta

Joseph R M Zbiciak

Methods, apparatus, systems and articles of manufacture to facilitate write miss caching in cache system are disclosed. An example apparatus includes a first cache storage; a second cache storage, wherein the second cache storage includes a first portion operable to store a first set of data evicted from the first cache storage and a second portion; a cache controller coupled to the first cache storage and the second cache storage and operable to: receive a write operation; determine that the write operation produces a miss in the first cache storage; and in response to the miss in the first cache storage, provide write miss information associated with the write operation to the second cache storage for storing in the second portion.

Methods and apparatus to facilitate write miss caching in cache system

In an example, a device includes a register file; a set of functional units coupled to the register file; and an instruction decoder coupled to the register file and to the set of functional units. The instruction decoder receives an executable instruction directed to a specific functional unit of the set of functional unit. The executable instruction includes a segment specifying a register of the register file. The instruction decoder also provides the executable instruction to the specific functional unit. The specific functional unit then determines whether to execute the executable instruction based on a value stored in the register of the register file specified by the segment of the executable instruction.

Conditional execution specification of instructions using conditional extension slots in the same execute packet in a VLIW processor

Techniques for maintaining cache coherency comprising storing data blocks associated with a main process in a cache line of a main cache memory, storing a first local copy of the data blocks in a first local cache memory of a first processor, storing a second local copy of the set of data blocks in a second local cache memory of a second processor executing a first child process of the main process to generate first output data, writing the first output data to the first data block of the first local copy as a write through, writing the first output data to the first data block of the main cache memory as a part of the write through, transmitting an invalidate request to the second local cache memory, marking the second local copy of the set of data blocks as delayed, and transmitting an acknowledgment to the invalidate request.

Delayed snoop for improved multi-process false sharing parallel thread performance

A system for handling requests that includes a set of memory banks coupled to a memory controller which comprises a set of read queues, including a read queue currently designated as the priority read queue. The memory controller loads read requests from an associated processor into the set of read queues. To process the read requests, the memory controller is configured to schedule the read requests of the priority read queue based on an availability of the associated memory bank, and if not in the priority read queue, also based on whether the read requests conflict with a recently scheduled read request from the priority read queue. Upon an execution of a read request from the priority read queue, the memory controller designates a different one of the set of read queues as the priority read queue, if the read request was at a front of the priority read queue.

Memory controller with command reordering

Methods, apparatus, systems and articles of manufacture are disclosed facilitate read-modify-write support in a coherent victim cache with parallel data paths. An example apparatus includes a random-access memory configured to be coupled to a central processing unit via a first interface and a second interface, the random-access memory configured to obtain a read request indicating a first address to read via a snoop interface, an address encoder coupled to the random-access memory, the address encoder to, when the random-access memory indicates a hit of the read request, generate a second address corresponding to a victim cache based on the first address, and a multiplexer coupled to the victim cache to transmit a response including data obtained from the second address of the victim cache.

Methods and apparatus to facilitate read-modify-write support in a coherent victim cache with parallel data paths

A method for performing a fundamental computational primitive in a device is provided, where the device includes a processor and a matrix multiplication accelerator (MMA). The method includes configuring a streaming engine in the device to stream data for the fundamental computational primitive from memory, configuring the MMA to format the data, and executing the fundamental computational primitive by the device.

Computational primitives using a matrix multiplication accelerator

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, and wherein the first instruction is configured to utilize a first memory location, begin execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction configured to utilize the first memory location, determining that the first instruction and the second instruction utilize the first memory location, and stalling execution of the second instruction based on the determining.

Entering protected pipeline mode without annulling pending instructions

In an example, a device includes a memory, a register, a data path including a set of lanes, and a processor that executes a program. The following operations are performed in response to execution of the program: write data to a field of the register, in which the data specifies that at least one lane of the set of lanes is powered on; execute an instruction on the at least one powered on lane; receive an interrupt; based on the interrupt, copy the data from the register to the memory; service the interrupt; and based on completing the service, copy data the data from the memory to the register.

Controlling the number of powered vector lanes via a register field

A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

Streaming engine with early and late address and loop count registers to track architectural state

Techniques for accessing memory by a memory controller, comprising receiving, by the memory controller, a memory management command to perform a memory management operation at a virtual memory address, translating the virtual memory address to a physical memory address, wherein the physical memory address comprises an address within a cache memory, and outputting an instruction to the cache memory based on the memory management command and the physical memory address.

Multicore shared cache operation engine

A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.

Butterfly network on load data return

A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Nested loop control

Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction for execution on an instruction execution pipeline, wherein the instruction execution pipeline is in a first execution mode, beginning execution of the first instruction on the instruction execution pipeline, receiving an execution mode instruction to switch the instruction execution pipeline to a second execution mode, switching the instruction execution pipeline to the second execution mode based on the received execution mode instruction, annulling the first instruction based on the execution mode instruction, receiving a second instruction for execution on the instruction execution pipeline, the second instruction, and executing the second instruction.

Entering protected pipeline mode with clearing

Methods, apparatus, systems and articles of manufacture to facilitate atomic operation in victim cache are disclosed. An example system includes a first cache storage to store a first set of data; a second cache storage to store a second set of data that has been evicted from the first cache storage; and a storage queue coupled to the first cache storage and the second cache storage, the storage queue including: an arithmetic component to: receive the second set of data from the second cache storage in response to a memory operation; and perform an arithmetic operation on the second set of data to produce a third set of data; and an arbitration manager to store the third set of data in the second cache storage.

Methods and apparatus to facilitate atomic operations in victim cache

A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and a cache controller configured to receive two or more cache commands, determine a conflict exists between the received two or more cache commands, determine a conflict resolution between the received two or more cache commands, and sending the two or more cache commands to the first sub-cache and the second sub-cache.

Victim cache with write miss merging

Growing community of inventors

University Park, TX, United States of America

Timothy David Anderson