Lsi Corporation

Lsi Logic Corporation

Timothy D Thompson

Christopher D Paulson

Steven Schauer

Kevin T Campbell

Richard Martin Born

David O Sluiter

Alan D Poeppelman

David A Thomas

Kevin Campbell

Mark Buchanan

Dongyan Jiang

Disclosed is a method for reducing latency between two clock domains in a digital electronic device. The time between a write to a queue position and a corresponding read of the queue position is reduced by up to one clock cycle by including a delay in the time before first writing data to a First In First Out (FIFO) queue used to buffer and synchronize data between two clock domains. The two clock domains have the same frequency, but may be out of phase. Reducing the latency between the write and the corresponding read reduces the required size of the FIFO queue and also results in more efficient system operation.

Method for reducing latency

A method for discarding perpetually-rejected packets in a fabric-based interconnect having a reliable physical layer is disclosed. A transmitting component keeps a count of the number of negative acknowledgements (NAKs) it receives from the receiving component for packets the transmitting component sends. If the transmitting component receives a number of consecutive NAKs for the same packet that exceeds some pre-determined threshold, the packet is not resent, but is, instead, treated as having been acknowledged, and subsequent packets are allowed to be transmitted. Higher-level processes are then notified of the problem so as to allow the error to be dealt with at a higher level, but without obstructing the flow of packets on the physical layer.

Method for discarding corrupted data packets in a reliable transport fabric

Disclosed is an adaptive method for training a source synchronous parallel receiver. The adaptive method for training, or aligning, parallel data channels permits a parallel communication receiver to adaptively adjust the timing of data channels to align the data channels with a frame channel and achieve a source synchronous signal for the parallel data channels. Further, portions of the frame channel training pattern may be used because possible time shift accuracy error is accounted for between the communication channels and a determination is made as to which portion of the frame pattern is currently being received. The data channels are then aligned appropriately.

Adaptive method for training a source synchronous parallel receiver

Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

Methods and apparatus for improved error and erasure correction in a Reed-Solomon date channel

A packetized data bus interface may be placed in a mode where data packets may be transmitted that are much larger than the standard packet size. The mode may allow the interface device and any other devices, networks, or transmission lines attached to the interface device to be more thoroughly exercised than previously able. The mode may be used for characterizing various aspects of the data interface.

Large transmissions on packetized data bus

An elasticity buffer has a reset input that, when activated, causes the elasticity buffer to temporarily cease operation. When the reset input bit is released, the elasticity buffer may resume operation. During periods when a device on a serial bus may be halted for power saving mode, for example, the serial communication may be reestablished and then the elasticity buffer may be released to continue operation.

Elasticity buffer restarting

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to store input data in response to a write pointer and present output data in response to a read pointer. The second circuit may be configured to generate a control signal in response to the write pointer, the read pointer and a type of an information packet containing the input data.

Active FIFO threshold adjustment

Disclosed is a method for minimizing the buffer size of an elasticity FIFO queue when synchronizing data between two clock domains. Data communication is typically sent by a transmitter device to a receiver device. The transmitted data signal includes an embedded clock signal and null data characters, as specified by the data communication signal protocol. A null character indicates an empty data frame and is included as part of most standard communication protocols. An embodiment skips one or more null characters from the elasticity FIFO queue during a single clock cycle when it is detected that the write pointer is catching up to the read pointer. By skipping multiple null characters during a single write cycle, the read pointer is moved ahead by one or more queue locations and the write pointer is insured to not catch up to the read pointer for a wider variation in frequencies between a transmitter and receiver than is normally possible. Typically, the elasticity FIFO queue size must be increased in order to support a larger frequency variation. By reducing the need to increase the elasticity FIFO queue size, the gate count and area needed for the elasticity FIFO queue on the silicon chip of the receiver is reduced, thus, reducing the cost contribution of the elasticity FIFO queue to the receiver device. Skipping null characters also reduces the latency time between a write and the associated read of a non-null data character.

Adaptive elasticity FIFO

A logical gate and a comparator are used to detect page boundaries in a data stream. A current address and a predetermined page size, that is an integer power of 2, are compared using a Boolean logic gate such as AND or XOR to detect a page boundary in a data stream. The output from the Boolean logic gate is compared to a predetermined value to cause a signal to be generated, indicating the end of the page.

Page boundary detector

An apparatus comprising one or more user programmable registers and a circuit configured to compare a predetermined portion of one or more information packets with contents of said one or more user programmable registers.

Method for receiving user defined frame information structure (FIS) types in a serial-ATA (SATA) system

A method and apparatus is provided for ensuring the integrity of data being transferred between two clock domains. Data is transferred on every clock signal from a faster clock domain to a slower clock domain. Data is collected by the data capture unit in two or more banks of registers for transfer to the second clock domain. The data collected has a first data size and is stacked with additional data of the first data size to generate data having a second data size. When two banks of registers are used, one bank of registers is being filled while the other bank of registers is passing data to the second clock domain. These two banks of registers provide two data paths to the synchronization logic for the second clock domain. This is especially advantageous when the limit of available bandwidth has been reached by one of the clock domains.

Method and apparatus for transferring data between a slower clock domain and a faster clock domain in which one of the clock domains is bandwidth limited

Apparatus, and an associated method, for generating multi-bit sequences used, for instance, to form an address pointer or a data pointer of a computer system. The circuitry is embodied in a single-cycle path and is operable to generate an output sequence which is of a bit length which is a multiple of an input sequence. In one implementation, the circuitry is used to generate 48-bit address pointers and 16-bit data pointers.

Apparatus, and associated method, for generating multi-bit length

A modular state machine, and associated method permits reuse of modular portions of the state machine. Instead of duplicating identical groups of states of the state machine, jumps are provided to a modular portion of the state machine formed of a group of states. The circuit area required to implement the state machine is thereby reduced.

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Windsor, CO, United States of America

Timothy D Thompson