Intel Corporation

Timothy D Low

Rachael Jade Parker

Hon-Mo Raymond Law

Matthew T Coe

An equalization circuit includes a detector to detect at least one bit pattern on a signal line and a transmit offset circuit to determine a phase-shift setting corresponding to the bit pattern detected by the detector. The phase-shift setting controls a delay in transmission of data on the signal line that suppresses noise including but not limited to inter-symbol interference.

System and method for performing adaptive phase equalization

Embodiments of the present invention describe methods and apparatuses for detecting signal loss in circuits such as a phase-locked loop (PLL). In one embodiment a PLL is equipped with detection logic to detect loss of a reference clock provided to the PLL and a feedback clock generated by the PLL.

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Beaverton, OR, United States of America

Timothy D Low