Cypress Semiconductor Corporation

Timothy D Jordan

Kamal Dalmia

Terry D Little

Bertrand Jeffery Williams

A method of synchronizing a clock signal to a data signal, comprising the steps of (A) detecting a first edge of the data signal and a position of the first edge, (B) determining if the position is within a zone, (C) if the edge is not within the zone, adjusting the clock signal towards the position of the edge, (D) detecting a second edge of the data signal and a position of the second edge, (E) determining a in value indicating a position of the second edge, (F) adding the first value to a second value, wherein the second value indicates a position of a third edge of the data signal and (G) adjusting the clock signal based on the result of step (F).

Linearized digital phase-locked loop

A method for synchronizing a clock signal to a data signal, comprising the steps of (A) detecting an edge of the data signal, (B) determining whether a position of the edge is within a zone and (B) if the edge is not within the zone, adjusting the clock signal towards the position of the edge.

Linearized digital phase-locked loop method

An apparatus for synchronizing a clock signal to a data signal. The apparatus comprises a detector and a control circuit. The detector may be configured to produce a value representing a position of an edge of said data signal based upon a state of said clock signal. The control circuit may be configured to adjust the clock signal based upon the value.

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Timothy D Jordan