Texas Instruments Corporation

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Texas Istruments Incorporated

Timothy D Dorney

Steven C Eplett

John E Riley

Anthony Michael Balistreri

Rishad S Omer

A method and apparatus delays an optical input using a scanning optical delay line. The scanning optical delay line includes an optical input and an optical output. A reflective element is arranged to rotate about an axis such that the reflective element maintains a constant incidence angle between the optical input and the reflective element for at least a portion of a rotation of the reflective element.

Scanning optical delay line using a reflective element arranged to rotate

A synchronous dynamic random access memory (SDRAM) improves memory access time by incorporating into the column address path a bidirectional column factor counter.

Synchronous random access memory having column factor counter for both

A method and apparatus for testing a semiconductor serial access memory (30) device through a main memory (20) includes a semiconductor memory comprising a main memory (20) and a serial access memory (30). A test data (48) is generated and an expected test data (50) that is equivalent to the test data (48) is also generated. The test data (48) is stored in the main memory and sent to the serial access memory (30). The test data (48) in the serial access memory is then sent back to the main memory (20) and stored in the main memory (20). The test data (48) is then read from the main memory (20). Then, the test data (48) read from the main memory is compared with the expected test data (50), producing an output having a first state if the test data (48) read from the main memory (20) is similar to the expected test data (50) or a second state if the test data (48) read from the main memory (20) is different than the expected test data (50).

Method and device for testing a semiconductor serial access memory

A sensing arrangement (100) for a dynamic random access memory (DRAM) is disclosed. The sensing arrangement (100) includes a sense amplifier bank (104) that is logically divided into a number of sense amplifier groups (106-1 to 106-2.sup.m). In a read operation, a given number of memory cells are coupled to the sense amplifier bank (104), and one sense amplifier group will provide read data while the remaining sense amplifier groups will refresh memory cell data. A timing circuit (102) receives a timing signal (EVAL) and address information (A1-Am) and in response thereto, enables the sense amplifier group that provides read data before the sense amplifier groups that refresh memory cell data. Peak current is reduced and improved sensing speed result.

Phased sense amplifiers

A reduced silicon area, wide input/output (I/O) comparitor method and apparatus for design-for-test applications includes a plurality of input/output pins (60) and plural arrays of addressable storage cells (32-46). A page mode writing circuit provides, through a common data-in lead (30), plural copies of a test data bit, applied through one of the pins (30), for storage in addressed storage cells (32-46) along a row in each of the arrays of storage cells. A circuit receives an expected data bit (ED), and a readout circuit reads out the stored test data bit from the addressed storage cells along the row in each of the arrays of storage cells. A PRW signal generator (154) responds to a column address change to establish a first potential state on all four quadrant-specific common lines (102, 408, 411, and 413). A plurality of multiplexer circuits (230), each multiplexer circuit associated with two different arrays of storage cells, are arranged to combine the multiple data bits from the associated arrays (32-46) to a reduced number of outputs to the plural comparitors circuits (242, 244, 248, and 250).

Method and apparatus for reducing area and pin count required in design

An integrated circuit memory device (21) includes plural input/output pins (30, 127 and others) and plural arrays of addressable storage cells (31-46). A set of circuits (51, 68, 70, 71-86, 90) provides access to a unique storage location in each array (31-46) through a given row and column address. A writing circuit (47, 68, 70, 71-86, 91-106, 131-146), designed for test, provides in parallel plural copies of a test data bit. The test data bit is applied through a single pin (30) and a common data-in lead (68), for storage in an addressed storage cell in each of the arrays. A readout circuit (110, 111, 112, 171, 127, 201-216, 131-146) is arranged for reading out the stored test data bit from the addressed storage cell in each of the arrays (31-46). The writing circuit, while in a block write test mode, stores the test data bit on the common data-in lead (68) in a block of address locations in each array (31-46).

Method and apparatus for a design for test, parallel block write

A semiconductor memory device (10) includes a plurality of row address inputs (RA0-RA8), and a plurality of column address input (CA0-CA8) lines. A plurality of main memory subarrays (122) include a plurality of memory cells (122). A plurality of redundant memory arrays are associated with the main memory arrays. Column redundancy circuitry (68) receives column addresses (CA3-CA7) for determining if a match occurs between the received column addresses and the stored redundant column information.

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Houston, TX, United States of America

Timothy D Dorney