Vitesse Semiconductor Corporation

Timothy Coe

Satish K Sridharan

Michael Jarchi

Ashish K Choudhury

Andrew Schmitt

Norm Hendrickson

Systems and methods for deskewing parallel data lines using at least one extra channel in parallel to the parallel data lines to carry data for comparing to data on the parallel data lines.

Data de-skew method and system

A method of synchronizing a transmitter and a receiver, comprising: receiving a transmitted serial data stream. Creating an N-bit data sample from the serial data stream. Decoding the N-bit data sample by a ring decoding technique. The ring decoding technique comprises: creating a first code ring using the N-bit data sample, the first code ring having N ring-bit phase positions corresponding to N axis positions, with the N data bits of the N-bit data sample corresponding to one of the N ring-bit phase positions. Creating a pth Code Ring from a previous code ring using a preselected ring coding technique, the pth code ring having N ring-bit phase positions corresponding to N axis positions, with N data bits of the pth code ring corresponding to the N ring-bit phase positions of the pth code ring. Analyzing selected ones of the N data bits of the pth code ring for the presence of a sentinel condition. Identifying a one of the N ring-bit phase positions of the pth code ring as being associated with the sentinel condition. Selecting a clock signal based on the one of the N ring-bit phase positions.

Fast locking clock and data recovery unit

A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decoder and multiple row encoders encoding a (255, 239) BCH code.

Product code based forward error correction system

An integrated circuit, having applicability to GaAs circuitry, is disclosed for performing a current steering logic function. The integrated circuit comprises a switching circuit, a high impedance tail current source, and a pair of low impedances respectfully coupled to the tail current source through a respective one of the switching transistors. The resistors in the tail current source and in the load resistance are formed from sheet resistor material so that any process-induced variation in the resistivity of the sheet material causes a mutual but compensatory variation in both the load and current source resistors, maintaining a match between the current capability of the current source and the resistance of the loads. The follower circuit, on the other hand, comprises a low impedance FET and a follower current source having an active load whose current is primarily dependent on its threshold voltage. Accordingly, process factors which affect the threshold voltage of the low impedance FET also affect the threshold voltage of the active load in a mutually compensatory manner without adversely affecting the output levels of the logic level signals from the current steering circuit.

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Oxnard, CA, United States of America

Timothy Coe