International Business Machines Corporation

Airbnb, Inc.

Timothy Clyde Buchholtz

Daniel Ramirez

Michael James Rohn

Morgan D Davis

Anthony Richard Bonaccio

Steven John Baumgartner

Sergey Vladimirovich Rylov

Karl Robert Erickson

George Francis Paulik

George Russell Zettles, Iv

Charles Porter Geer

Dana Marie Woeste

Timothy Lindquist

Jarrett Betke

Daniel Mark Dreps

Mounir Meghelli

David W Siljenberg

Daniel Guy Young

Giri N Rangan

Rajesh Cheeranthodi

Andrew Benson Maki

Layne A Berge

Thomas W Liang

Kevin O'Connell

Raymond Alan Richetta

Andrew Douglas Davies

Nghia Van Phan

Timothy Joseph Schmerbeck

Thomas Pham

Michael R Gruver

Kevin Daniel Escobar

A cable connector for counting a number of plug-in events and preventing further plug in attempts after a threshold number of plug-in events have occurred. An inner sleeve is located inside an outer sleeve, and is designed to move relative to the outer sleeve. The inner sleeve further includes a tab on an outer surface of the inner sleeve. A gear wheel is located inside the outer sleeve and perpendicular to the inner sleeve and has a number of gear teeth. A toggle plug counter rotates the gear wheel one tooth in response to a plug-in action of the cable counter. When the gear wheel rotates to a point where the tab aligns with a notch in the gear wheel an inner spring at the opposite end of the inner sleeve causes the inner sleeve to move through the gear wheel such that further plugging action becomes difficult.

Plug count limiter for cables

One or more systems, devices, and/or methods provided herein relate to a process for in-process radio frequency (RF) signal quality analysis and amplitude adjustment of one or more RF devices. In one or more embodiments, the RF device can comprise a portion of a quantum computing system, such as of readout electronics thereof, and thus amplitude adjustment can be at a waveform generator that generates pulses to affect one or more qubits of a quantum logic circuit of the quantum computing system. Generally, an electronic device can comprise an RF tap connected to an RF signal component of a first RF signal chain, and an analysis component connected to the RF tap, the analysis component configured to convert an RF signal from the RF signal component and to compare a conversion result thereof to an expected power output that is based on historical data for a second RF signal chain.

Radio frequency signal integrity verification

An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

Distortion reduction circuit

Authentication includes receiving an indication of physical possession of a payment card by a merchant and receiving a purchase request for an authorization of an exchange from the payment account of the cardholder to the merchant. Authentication includes assigning a randomized transaction identifier to the request for the authorization of the exchange. The method also includes transmitting the request for the authorization of the exchange from the payment account of the cardholder to the merchant and receiving the assigned randomized transaction identifier and a randomized authentication identifier associated with the randomized transaction identifier from a payment association, the payment association determining whether the request for the authorization of the exchange is valid. Authentication includes transmitting a copy of the randomized authentication identifier to the mobile device and receiving validation that the transmitted copy of the randomized authentication identifier from the mobile device matches the randomized authentication identifier.

Multi-point authentication for payment transactions

Authentication for payment transaction includes receiving, by a point-of-sale (POS) terminal, an indication that a payment account of a cardholder is associated with a mobile device and receiving a second indication of physical possession of a payment card by a merchant. The authentication includes receiving a purchase request for an authorization of exchange from the payment account of the cardholder to the merchant and assigning a transaction identifier to the request for the authorization of the exchange. The authentication includes transmitting the request for authorization of the exchange from the cardholder payment account to the merchant and the transaction identifier. The authentication includes receiving an indication that an authentication identifier is associated with the transaction identifier. The authentication includes receiving a copy of the authentication identifier, facilitated by the cardholder. The authentication includes receiving validation that the copy of the authentication identifier matches the authentication identifier.

Authentication includes determining that a cardholder payment account is associated with a mobile device. Authentication includes receiving an indication of physical possession of a payment card. Authentication includes receiving a purchase request for an authorization of an exchange of funds from the cardholder account to the merchant. Authentication includes receiving a randomized transaction identifier to the request for the authorization of the exchange. Authentication includes transmitting to the mobile device, information associated with the request. Authentication includes transmitting to the mobile device, a request for confirmation of the authorization from the cardholder from the account of the cardholder to the merchant. Authentication includes receiving an indication, facilitated by the cardholder, that the exchange is authorized. Authentication includes authorizing the exchange of from the payment account of the cardholder to the merchant.

System, method and computer program product for setting phase control codes to (in-phase) I and (quadrature) Q rotators to a first code pair, different by enough to produce a phase difference between the rotator outputs sufficient to be detected with minimal error by a phase-to-voltage converter. Auxiliary trim DACs are then adjusted according to calibration logic until a comparator output detects a phase difference between the I and Q rotators are within tolerable limits. The resulting trim codes are stored for both the codes in the pair. These trim codes along with the main codes are subsequently applied whenever the codes are used thereafter. These steps are repeated with each successive code pair having the same separation as the first code pair, e.g. both incremented by same amount until all codes have been calibrated. In this manner having the phase separation between all code pairs forced to the same value.

Phase interpolator calibration

A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Architecture for a physical interface of a high speed front side bus

A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.

Unlock mode in source synchronous receivers

A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Growing community of inventors

Rochester, MN, United States of America

Timothy Clyde Buchholtz