International Business Machines Corporation

Timothy Carl Bronson

Pak-kin Mak

Michael Andrew Blake

Garrett M Drapala

Hieu Trong Huynh

Vesselina K Papazova

Gregory William Alexander

Robert J Sonnelitter, Iii

Craig Raymond Walters

Kenneth Douglas Klapproth

Christian Jacobi

Ekaterina M Ambroladze

Jason D Kohl

Michael F Fee

Phillip G Williams

Deanna Postles Dunn Berger

Tu-An T Nguyen

Richard Joseph Branciforte

Winston Herring

Matthias Klein

Aaron Tsai

Glenn David Gilda

Guy G Tracy

Hanno Ulrich

Vincent P Zeyak, Jr

Ashraf ElSharif

John M Sheplock

Wai Ling Lee

Vijayalakshmi Srinivasan

Bruce Leroy Beukema

Ronald Edward Fuhs

Scott Barnett Swaney

Arthur J O'Neill

Arthur J O'Neill, Jr

Stefan P Jackowski

Akash V Giri

Rebecca Marie Gott

Ram Sai Manoj Bamdhamravuri

Chung-Lung K Shum

Mark S Farrell

Patrick James Meaney

Markus Kaltenbach

Anthony J Bybell

Gary E Strait

William J Lewis

Eyal Naor

Lawrence D Curley

Deanna P Berger

Charlie Chornglii Hwang

Deanna P D Berger

Yair Fried

Bruce George Rudolph

William Garrett Verdoorn, Jr

Lior Binyamini

Taylor J Pritchard

Lahiruka Winter

Chunggeon Rhee

David Andrew Thorndike

Robert Sonnelitter

A lower-level cache managing cross-core invalidation (XI) snapshots in a shared-memory multiprocessing system, wherein the management of XI snapshots reduces an amount of required snapshots while allowing shared lower-level caches, comprising: the lower-level cache maintaining respective response sync state for at least one processor in a plurality of processors signifying that a line may have been changed by another processor since last fetched by a requesting processor.

Cross-core invalidation snapshot management

Castout handling in a distributed cache topology, including: detecting, by a first cache of a plurality of caches, a cache miss; providing, by the first cache to each other cache of the plurality of caches, a message comprising: data indicating a cache address corresponding to the cache miss; and data indicating a cache line to be evicted.

Castout handling in a distributed cache topology

Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Decentralized hot cache line tracking fairness mechanism

A node of the computing environment obtains an exclusive fetch request of a cache line shared by, at least, the node and a manager node of the computing environment. The exclusive fetch request includes a state indication regarding processing of the exclusive fetch request by the manager node. The node processes the exclusive fetch request, based on the state indication included with the exclusive fetch request regarding processing of the exclusive fetch request by the manager node.

Invalidity protection for shared cache lines

A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

Shadow pointer directory in an inclusive hierarchical cache

A method for managing designated authority status in a cache line includes identifying an initial designated authority (DA) member cache for a cache line, transferring DA status from the initial DA member cache to a new DA member cache, determining whether the new DA member cache is active, indicating a final state of the initial DA cache responsive to determining that the new DA member cache is active, and overriding a DA state in a cache control structure in a directory. A method for managing cache accesses during a designated authority transfer includes receiving a designated authority (DA) status transfer request, receiving an indication that a first cache will invalidate its copy of the cache line, allowing a second cache to assume DA status for the cache line, and denying access to the first cache's copy of the cache line until invalidation by the first cache is complete.

Final cache directory state indication

A computer-implemented method is provided. The method includes determining whether a rejection of a request is required and determining whether the request is software forward progress (SFP)-likely or SFP-unlikely upon determining that the rejection of the request is required. The method also includes executing a first pseudo random decision to set or not set a requested state of the request in an event the request is SFP-likely or SFP-unlikely, respectively, and rejecting the request following execution of the second pseudo random decision.

Hot line fairness mechanism favoring software forward progress

Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.

Using a shadow copy of a cache in a cache hierarchy

A primary controller has authority of a cache line associated with a fetch and manages a second cache line request from a different and non-associated secondary requesting entity. A secondary controller, associated with the secondary requesting entity, is granted authority of the cache line and further manages multiple subsequent simultaneous or overlapping requests for the cache line from different non-associated subsequent requesting entities by maintaining authority of the cache line, by granting read-only access to the cache line to respective subsequent controllers, each associated with a different subsequent requesting entity, and by passing a non-authority token to each of the respective subsequent controllers.

Multiprocessor system cache management with non-authority designation

A method and a computer system for core recovery management are provided. A first operation signal is generated via a first hardware agent. The first operation signal indicates that the first hardware agent is processing an operation requested by a first processor core. The first processor core receives a first extend fence signal based on the generated first operation signal. As long as the first extend fence signal is received via the first processor core, the first processor core is kept in a fenced state for core recovery.

Preventing extraneous messages when exiting core recovery

Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.

Lateral persistence directory states

Aspects of the invention include computer-implemented methods, systems, and computer program products that access a multi-copy scope directory state of a cache memory that indicates a scope of sharing of a cache line in a cache memory system and determine a scope of sharing of the cache line in the cache memory system based on the multi-copy scope directory state, where the multi-copy scope directory state enumerates a plurality of scopes within the cache memory system. The scope of sharing is used to reduce a number of queries to one or more cache memories having a larger scope than a shared scope identified in the scope of sharing. The multi-copy scope directory state of the cache memory is updated based on detecting a change in shared scope of the cache line within the cache memory system.

Multiple copy scoping bits for cache memory

Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Dual clusters of fully connected integrated circuit multiprocessors with shared high-level cache

A cache coherency management facility to reduce latency in granting exclusive access to a cache in certain situations. A node requests exclusive access to a cache line of the cache. The node is in one region of nodes of a plurality of regions of nodes. The one region of nodes includes the node requesting exclusive access and another node of the computing environment, in which the node and the another node are local to one another as defined by a predetermined criteria. The node requesting exclusive access checks a locality cache coherency state of the another node, the locality cache coherency state being specific to the another node and indicating whether the another node has access to the cache line. Based on the checking indicating that the another node has access to the cache line, a determination is made that the node requesting exclusive access is to be granted exclusive access to the cache line. The determining being independent of transmission of information relating to the cache line from one or more other nodes of the one or more other regions of nodes.

Granting exclusive cache access using locality cache coherency state

Growing community of inventors

Round Rock, TX, United States of America

Timothy Carl Bronson