Texas Instruments Corporation

Timothy Bryan Merkin

Hassan Pooya Forghani-Zadeh

Byungchul Jang

Orlando Lazaro

John Russell Broze

Susan A Curtis

Nghia Trong Tang

Brent Alan McDonald

Salvatore Giombanco

Harish Venkataraman

Ariel Dario Moctezuma

Erick Omar Torres

Joseph Michael Leisten

Nan Xing

Michael Ryan Hanschke

Michael James Mills

Karan Singh Jain

Anand Devendra Kudari

Fan Wang

Biasing an isolation region in a semiconductor substrate. An integrated circuit includes a semiconductor substrate, a first rectifying device, and a second rectifying device. The semiconductor substrate has a first region, a second region, and a third region each being an opposite conductivity type from the semiconductor substrate. The first region and the second region are respective current terminals of a transistor. The first rectifying device has a first positive terminal and a first negative terminal. The first positive terminal is coupled to the first region, and the first negative terminal is coupled to the third region. The second rectifying device has a second positive terminal and a second negative terminal. The second positive terminal is coupled to a ground terminal, and the second negative terminal is coupled to the third region.

Biasing isolation region in semiconductor substrate

An electronic device has a first circuit, a second circuit, and an isolation circuit, the isolation circuit having an input and an output, the first circuit including a signal generator having an output, the output of the signal generator coupled to the input of the isolation circuit. The second circuit includes a rectifier circuit and a signal detector circuit, the rectifier circuit having a rectifier input coupled to the output of the isolation circuit, and the signal detector circuit having an input coupled to the output of the isolation circuit.

Rectifier with signal reconstruction

A switched capacitor voltage multiplication device has a rectifier with a DC input terminal and a DC output terminal and two pulse input terminals. A first flying capacitor is coupled to one of the pulse input terminals, while a second flying capacitor is coupled to the other pulse input terminal. A recycle resistor is coupled across the rectifier with a first resistor terminal coupled to one pulse input terminal and a second resistor terminal coupled to the other pulse input terminal.

Switched capacitor circuit with passive charge recycling

In described examples of a circuit that operates as a low-power ideal diode, and an IC chip that contains the ideal diode circuit, the circuit includes: a first P-channel transistor connected to receive an input voltage on a first terminal and to provide an output voltage on a second terminal; a first amplifier connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the first P-channel transistor as a function of the voltage across the first P-channel transistor; and a second amplifier connected to receive the input voltage and the output voltage and to provide a second signal that acts to turn off the gate of the first P-channel transistor responsive to the input voltage being less than the output voltage.

Low power ideal diode control circuit

An integrated circuit (IC) comprises an output and a voltage regulator. The voltage regulator comprises an amplifier having a first input coupled to a reference voltage source and a second input coupled to the output, a first resistor coupled to the output and coupled to a ground terminal, a metal oxide semiconductor field effect transistor (MOSFET) having a gate coupled to an output of the amplifier and a drain coupled to the output, and a second resistor coupled to a source of the MOSFET and coupled to the ground terminal.

Voltage regulator in USB power delivery integrated circuit

An apparatus includes an amplifier configured to compare a feedback input, corresponding to a voltage of an output voltage node, with respect to a reference input and to provide a control output to control the output voltage node based on a difference between the feedback input and the reference input. At least two source circuits are coupled with the output voltage node. Each of the source circuits are configured to provide respective voltage sources to supply electrical power to the output voltage node.

Multi-input voltage regulator

USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state.

Circuit and method for interfacing universal serial bus

A current mirror includes a first pair of transistors, wherein gates of the first pair of transistors are connected together, and a second pair of transistors coupled to the first pair of transistors. Gates of the second pair of transistors are connected together. A first resistive device is coupled across a drain and a source of one of the transistors of the second pair of transistors. A second resistive device is coupled across a drain and a source of the other transistor of the second pair of transistors. The first pair of transistors are configured to operate in weak inversion at an input current to the current mirror within a first current range and the second pair of transistors are configured to operate in strong inversion at an input current within a second current range.

Large range current mirror

Protection circuits, USB interface integrated circuits, and methods for protecting host circuitry from USB port pin overvoltages, in which a switch is connected between a USB port pin and a middle node, and a detection circuit compares the middle node voltage with a reference voltage. A control circuit turns off the switch and turns on a clamp circuit to conduct pull down current from the middle node in response to the middle node voltage exceeding the reference voltage to mitigate overvoltage conditions on a host pin coupled to the middle node. When the middle node voltage falls below the reference voltage, the control circuit delays for a predetermined time and then turns off the clamp circuit and turns on the switch.

Overvoltage protection circuit for USB interface

An LLC converter includes an input having a first node and a second node. A first switch is coupled between the first node and a third node and a second switch is coupled between the third node and the second node. A transformer having a first transformer input is coupled to the third node. A resonant capacitor is coupled to a second transformer input and a first input of a summer. A voltage ramp generator is coupled to a second input of the summer, the summer for summing voltages at the first input and the second input. The converter further includes circuitry for generating control signals for the first switch and the second switch in response to the output of the summer.

Hybrid hysteretic control for LLC converter

Disclosed examples include ICs and general-purpose I/O circuitry to facilitate interfacing of the IC with a variety of external circuits operating at different supply voltages, in which an integer number N supply drive circuits are individually coupled with a corresponding supply voltage node and selectively connect the corresponding supply voltage node to a general-purpose output node based on a supply drive control signal to allow programmable interfacing of individual general-purpose output pads or pins of the IC with an external circuit at the appropriate signal level.

Multi-supply output circuit

A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

Method, apparatus and system for an edge rate controlled output buffer

A circuit that operates as a low-power ideal diode is disclosed, as well as an IC chip that contains the ideal diode circuit. The circuit includes a first P-channel transistor connected to receive an input voltage on a first terminal and to provide an output voltage on a second terminal, a first amplifier connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the first P-channel transistor as a function of the voltage across the first P-channel transistor, and a second amplifier connected to receive the input voltage and the output voltage and to provide a second signal that acts to turn off the gate of the first P-channel transistor responsive to the input voltage being less than the output voltage.

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Richardson, TX, United States of America

Timothy Bryan Merkin