Microunity Systems Engineering, Inc.

Broadcom Corporation

Broadcom Homenetworking, Inc.

Timothy B Robinson

Dane Snow

Alan G Corry

Larry C Yamano

Edward H Frank

Tracy D Mallory

Craig Stephen Forrest

John T Holloway

Kevin H Peterson

William K Zuravleff

Craig C Hansen

Mark Semmelmeyer

Scott Furman

Jason A Trachewsky

John Gray Campbell

A receiver circuit of the modem is coupled to receive a continuous analog signal from a communication channel. This analog signal includes both packet and idle information. A burst mode protocol is also provided, in which packets of digital information are modulated by a transmitter circuit of the modem, thereby converting the packets of digital information into analog signal bursts of discrete duration. These analog signal bursts are transmitted from the transmitter circuit to a telephone line. A receiver circuit monitors the telephone line to detect the analog signal bursts. Upon detecting the presence of the analog signal bursts on the telephone line, the receiver circuit demodulates the analog signal bursts using full processing capabilities of the receiver circuit. However, upon detecting the absence of the analog signal bursts on the telephone line, the demodulating function of the receiver circuit is disabled. The burst mode protocol enables multi-drop and multi-cast operation, as well as reducing required DSP resources.

Method and apparatus for reducing signal processing requirements for transmitting packet-based data

A multiplexing scheme to select either an I component or a Q component for input to I channel and Q channel inputs of a baseband receiver. The selection of which of the I or Q component to place on the I channel input and which other to place on the Q channel input is based on, there being a correct relationship of the I and Q components received from a RF processing stage of a wireless communication device or if the I and Q components have incorrect relationship because they are interchanged.

Programmable identity of I and Q channels

A method of and apparatus for noise reduction for a transceiver transmitting frames over a transmission medium in a frame-based communications network. A transceiver transmit path and a transceiver receive path is provided. A blocking switch is located in the transceiver transmit path, the blocking switch allowing transmit signal propagation when enabled, while preventing both transmit signal propagation and circuit device noise coupling from the transceiver transmit path to the transceiver receive path when the blocking switch is disabled. The blocking switch is disabled when the transceiver transmit path is not transmitting frames over the frame-based communications network.

Method and apparatus for transceiver noise reduction in a frame-based communications network

A method of and apparatus for optimizing signal transformation from a twisted pair transmission line to a combination transmitter and receiver for a frame-based communications network, the transmitter having a transmit output pair port for transmitting signals onto the frame-based communications network over the twisted pair transmission line, the receiver having a receive input pair port for receiving signals from the frame-based communications network over the twisted pair transmission line. A transformer is coupled between the twisted pair transmission line and each of the transmit output pair port and the receive input pair port. The transformer has a coil across the twisted pair, a transmit coil across the transmit output pair port, and a receive coil across the receive input pair port. A transfer ratio between the transmit coil and the coil across the twisted pair is optimized for transmitting signals. A transfer ratio between the receive coil and the coil across the twisted pair is optimized for receiving signals.

Method and apparatus for optimizing signal transformation in a frame-based communications network

A modem and method for operating same. A receiver circuit of the modem is coupled to receive a continuous analog signal from a communication channel. This analog signal includes both packet and idle information. The receiver circuit monitors the analog signal to detect the presence of idle information. Upon detecting idle information, the receiver circuit enters a standby mode in which the processing requirements of the receiver circuit are reduced. A burst mode protocol is also provided, in which packets of digital information are modulated by a transmitter circuit of the modem, thereby converting the packets of digital information into analog signal bursts of discrete duration. These analog signal bursts are transmitted from the transmitter circuit to a telephone line. However, the transmitter circuit does not generate any signals between the analog signal bursts. A receiver circuit monitors the telephone line to detect the analog signal bursts. Upon detecting the presence of the analog signal bursts on the telephone line, the receiver circuit demodulates the analog signal bursts using full processing capabilities of the receiver circuit. However, upon detecting the absence of the analog signal bursts on the telephone line, the demodulating function of the receiver circuit is disabled. The burst mode protocol enables multi-drop and multi-cast operation, as well as reducing required DSP resources.

Method and apparatus for reducing signal processing requirements for transmitting packet-based data with a modem

A digital differential analyzer data synchronizer receives data at a first clock rate and synchronizes the data to a second clock rate. The two clock rates are related by a ratio of two integers, but have a variable phase relationship. The synchronizer places incoming data into a series of registers at the first clock rate. A digital differential analyzer functions to generate a synchronization signal having a frequency proportional to a ratio of the first clock rate and the second clock rate. A multiplexer is utilized for sequentially reading the plurality of registers at a rate corresponding to the frequency of the synchronization signal.

Digital differential analyzer data synchronizer

Method and apparatus for reducing signal processing requirements for

A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

Method for storing prioritized memory or I/O transactions in queues

A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

Non-blocking load buffer and a multiple-priority memory system for

A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access commands, and generates memory access responses. The interface includes a data path, and a number of memory controllers. The interface receives and transmits input and output data streams, and the memory controllers control the flow of the input and output data streams within the memory chip. A packet buffer is coupled between the data path and the memory device. The packet buffer provides for temporary storage of memory access commands, response information, and forwarding data.

DRAM with high bandwidth interface that uses packets and arbitration

System for placing entries of an outstanding processor request into a

A controller for a synchronous DRAM is provided for maximizing throughput of memory requests to the synchronous DRAM. The controller maintains the spacing between the commands to conform with the specifications for the synchronous DRAMs while preventing gaps from occurring in the data slots to the synchronous DRAM. Furthermore, the controller allows memory requests and commands to be issued out of order so that the throughput may be maximized by overlapping required operations which do not specifically involve data transfer. To achieve this maximized throughput, memory requests are tagged for indicating a sending order. Thereafter, the memory requests may be arbitrated when conflicting memory requests are queued and this arbitration process is then decoded for simultaneously updating scheduling constraints. The memory requests may be further qualified based on the scheduling constraints and a command stack of memory request is then developed for modifying update queues. The controller also functions by receiving a controller clock signal and generating an SDRAM clock signal by dividing this controller clock signal.

Controller for a synchronous DRAM that maximizes throughput by allowing

A large burst mode memory accessing system includes N discrete sub-memories and three main I/O ports. Data is stored in the sub-memories so that the sub-memories are accessed depending on their proximity to the main I/O ports. Three parallel pipelines provide a data path to/from the main I/O ports and the sub-memories. The first pipeline functions to couple address/control signals to the memories such that adjacent sub-memories are accessed in half cycle intervals. The second pipeline functions to propagate accessed data from the sub-memories to the main I/O ports such that data is outputted from the main output port every successive clock cycle. The third pipeline propagates write data to the memories such that data presented at the input of the third pipeline on successive clock cycles is written into successive sub-memories. Redundancy circuits preserve data integrity without memory access interruption.

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Boulder Creek, CA, United States of America

Timothy B Robinson